Integrated circuit with millimeter wave and inductive coupling and methods for use therewith

ABSTRACT

A circuit includes a plurality of integrated circuits or dies having corresponding circuits, the plurality of integrated circuits or dies include a first plurality of integrated circuits or dies having corresponding millimeter wave interfaces and a second plurality of integrated circuits or dies having corresponding inductive interfaces. The first plurality of integrated circuits or dies communicate first signals therebetween via the corresponding millimeter wave interfaces and the second plurality of integrated circuits or dies communicate second signals therebetween via the corresponding inductive interfaces.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present U.S. Utility Patent Application claims priority pursuant to35 U.S.C. §121, as a divisional, to the U.S. Utility patent applicationSer. No. 12/040,301, entitled INTEGRATED CIRCUIT WITH MILLIMETER WAVEAND INDUCTIVE COUPLING AND METHODS FOR USE THEREWITH, filed on Feb. 29,2008, which is hereby incorporated herein by reference in its entiretyand made part of the present U.S. Utility Patent Application for allpurposes.

The present application is related to the following patent applicationsthat are commonly assigned:

U.S. application Ser. No. 12/038,260, entitled, INDUCTIVELY COUPLEDINTEGRATED CIRCUIT AND METHODS FOR USE THEREWITH, filed on Feb. 27,2008, issued as U.S. Patent No. 7,750,435 on Jul. 6, 2010;

U.S. application Ser. No. 12/039,256, entitled, INDUCTIVELY COUPLEDINTEGRATED CIRCUIT WITH MAGNETIC COMMUNICATION PATH AND METHODS FOR USETHEREWITH, filed on Feb. 28, 2008, issued as U.S. Pat. No. 7,795,700 onSep. 14, 2010; U.S. application Ser. No. 12/041,463, entitled,INDUCTIVELY COUPLED INTEGRATED CIRCUIT WITH NEAR FIELD COMMUNICATION ANDMETHODS FOR USE THEREWITH, filed on Mar. 3, 2008, abandoned; and

U.S. application Ser. No. 12/041,723, entitled, INDUCTIVELY COUPLEDINTEGRATED CIRCUIT WITH MULTIPLE ACCESS PROTOCOL AND METHODS FOR USETHEREWITH, filed on Mar. 4, 2008.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

This invention relates generally to integrated circuits and couplingmethods used therein.

2. Description of Related Art

As IC fabrication technology continues to advance, ICs will becomesmaller and smaller with more and more transistors. While thisadvancement allows for reduction in size of electronic devices, it doespresent a design challenge of providing and receiving signals, data,clock signals, operational instructions, etc., to and from a pluralityof ICs of the device. Currently, this is addressed by improvements in ICpackaging and multiple layer PCBs. For example, ICs may include aball-grid array of 100-200 pins in a small space (e.g., 2 to 20millimeters by 2 to 20 millimeters). A multiple layer PCB includestraces for each one of the pins of the IC to route to at least one othercomponent on the PCB. Clearly, advancements in communication between ICsare needed to adequately support the forth-coming improvements in ICfabrication.

Wireless communication devices include a built-in radio transceiver(i.e., receiver and transmitter) or is coupled to an associated radiotransceiver (e.g., a station for in-home and/or in-building wirelesscommunication networks, RF modem, etc.). As is known, the receiver iscoupled to the antenna and includes a low noise amplifier, one or moreintermediate frequency stages, a filtering stage, and a data recoverystage. The low noise amplifier receives inbound RF signals via theantenna and amplifies then. The one or more intermediate frequencystages mix the amplified RF signals with one or more local oscillationsto convert the amplified RF signal into baseband signals or intermediatefrequency (IF) signals. The filtering stage filters the baseband signalsor the IF signals to attenuate unwanted out of band signals to producefiltered signals. The data recovery stage recovers raw data from thefiltered signals in accordance with the particular wirelesscommunication standard.

As is also known, the transmitter includes a data modulation stage, oneor more intermediate frequency stages, and a power amplifier. The datamodulation stage converts raw data into baseband signals in accordancewith a particular wireless communication standard. The one or moreintermediate frequency stages mix the baseband signals with one or morelocal oscillations to produce RF signals. The power amplifier amplifiesthe RF signals prior to transmission via an antenna.

In most applications, radio transceivers are implemented in one or moreintegrated circuits (ICs), which are inter-coupled via traces on aprinted circuit board (PCB). The radio transceivers operate withinlicensed or unlicensed frequency spectrums. For example, wireless localarea network (WLAN) transceivers communicate data within the unlicensedIndustrial, Scientific, and Medical (ISM) frequency spectrum of 900 MHz,2.4 GHz, and 5 GHz.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operationthat are further described in the following Brief Description of theDrawings, the Detailed Description of the Invention, and the claims.Other features and advantages of the present invention will becomeapparent from the following detailed description of the invention madewith reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S)

FIG. 1 is a schematic block diagram of an embodiment of an electronicdevice 10 in accordance with the present invention;

FIG. 2 is a schematic block diagram of an embodiment of integratedcircuits 20 and 24 in accordance with the present invention;

FIG. 3 is a schematic block diagram of an embodiment of inductiveinterfaces 22 and 26 in accordance with the present invention;

FIG. 4 presents a schematic block diagram representation of anintegrated circuit 16 in accordance with an embodiment of the presentinvention;

FIG. 5 presents a schematic block diagram representation of anintegrated circuit 17 in accordance with an embodiment of the presentinvention;

FIG. 6 present pictorial representations of a top view of on-chip coil330 in accordance with an embodiment of the present invention;

FIG. 7 present pictorial representations of a side view of on-chip coil330 in accordance with an embodiment of the present invention;

FIG. 8 present pictorial representations of a bottom view of on-chipcoil 330 in accordance with an embodiment of the present invention;

FIG. 9 is a schematic block diagram of an embodiment of RF transceiver135 in accordance with the present invention;

FIG. 10 presents a schematic block diagram representation of anintegrated circuit 18 in accordance with an embodiment of the presentinvention;

FIG. 11 is a schematic block diagram of an embodiment of integratedcircuit dies 30 and 34 in accordance with the present invention;

FIG. 12 is a schematic block diagram of magnetic communication path 98in accordance with an embodiment the present invention;

FIG. 13 is a schematic block diagram of magnetic communication path 98′in accordance with another embodiment the present invention;

FIG. 14 is a pictorial representation of a side view of integratedcircuit 325 in accordance with an embodiment the present invention;

FIG. 15 is a pictorial representation of a bottom view of integratedcircuit 325 in accordance with an embodiment the present invention;

FIG. 16 is a pictorial representation of integrated circuit 19 inaccordance with an embodiment the present invention;

FIG. 17 is a pictorial representation of integrated circuit 51 inaccordance with an embodiment the present invention;

FIG. 18 is a schematic block diagram of an embodiment of integratedcircuits 40 and 44 in accordance with the present invention;

FIG. 19 is another schematic block diagram of an embodiment ofintegrated circuits 40 and 44 in accordance with the present invention;

FIG. 20 is a schematic block diagram of an embodiment of integratedcircuits 40, 41 and 43 in accordance with the present invention;

FIG. 21 is a pictorial representation of integrated circuit 71 inaccordance with an embodiment the present invention;

FIG. 22 is a pictorial representation of integrated circuit 73 inaccordance with an embodiment the present invention;

FIG. 23 is a pictorial and block diagram representation of electronicdevice 80 in accordance with an embodiment the present invention;

FIG. 24 is a schematic block diagram of an embodiment of RF transceiver1035 in accordance with the present invention;

FIG. 25 is schematic block diagram of an embodiment of integratedcircuits 60 and 24 in accordance with the present invention;

FIG. 26 is a pictorial representation of integrated circuit 75 inaccordance with an embodiment the present invention;

FIG. 27 is a schematic block diagram of an embodiment of an RFID tag inaccordance with the present invention;

FIGS. 28-29 are schematic block diagrams of other embodiments of adevice in accordance with the present invention;

FIG. 30 is a diagram of an embodiment of a frame of an intra-devicewireless communication in accordance with the present invention;

FIGS. 31-35 are schematic block diagrams of other embodiments of adevice in accordance with the present invention;

FIGS. 36-38 are schematic block diagrams of embodiments of an RFtransceiver device in accordance with the present invention;

FIG. 39 is a diagram of an example of a frame of an RF transceiverdevice wireless communication in accordance with the present invention;

FIG. 40 is a logic diagram of an embodiment of a method of resourceallocation for an intra-device wireless communication in accordance withthe present invention;

FIG. 41 is a diagram of another example of a frame of an RF transceiverdevice wireless communication in accordance with the present invention;

FIG. 42 is a diagram of an example of mapping data of an RF transceiverdevice wireless communication in accordance with the present invention;

FIGS. 43 and 44 are schematic block diagrams of other embodiments of anRF transceiver device in accordance with the present invention;

FIG. 45 is a schematic block diagram of another embodiment of an RFIDsystem in accordance with the present invention;

FIG. 46 is a schematic block diagram of another embodiment of an RFIDsystem in accordance with the present invention;

FIG. 47 is a schematic block diagram of an embodiment of an RFID readerin accordance with the present invention;

FIG. 48 is a schematic block diagram of another embodiment of a devicein accordance with the present invention;

FIG. 49 is a logic diagram of a method for switching within a deviceaccordance with the present invention;

FIG. 50 is a schematic block diagram of an embodiment of an RF buscontroller in accordance with the present invention;

FIG. 51 is a logic diagram of method for controlling access to an RF busin accordance with the present invention;

FIG. 52 is a diagram of another embodiment of a frame of an RF buscommunication in accordance with the present invention;

FIG. 53 is a logic diagram of method for determining RF bus resourceavailability in accordance with the present invention;

FIG. 54 is a logic diagram of another method for controlling access toan RF bus in accordance with the present invention;

FIG. 55 is a schematic block diagram of another embodiment of a devicein accordance with the present invention;

FIG. 56 is a logic diagram of another method for controlling access toan RF bus in accordance with the present invention;

FIG. 57 is a logic diagram of another method for controlling access toan RF bus in accordance with the present invention;

FIG. 58 is a schematic block diagram of an embodiment of an RF bustransceiver in accordance with the present invention;

FIG. 59 is a logic diagram of method for RF bus transmitting inaccordance with the present invention;

FIG. 60 is a logic diagram of method for RF bus receiving in accordancewith the present invention;

FIG. 61 is a logic diagram of method for determining whether informationis to be transmitted via an RF bus in accordance with the presentinvention;

FIG. 62 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 63 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 64 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 65 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 66 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 67 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 68 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 69 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 70 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 71 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 72 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 73 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 74 is a flowchart representation of a method in accordance with anembodiment of the present invention;

FIG. 75 is a flowchart representation of a method in accordance with anembodiment of the present invention; and

FIG. 76 is a flowchart representation of a method in accordance with anembodiment of the present invention;

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic block diagram of an embodiment of an electronicdevice 10 in accordance with the present invention. In particular, anelectronic device 10 is presented that includes inductively coupledintegrated circuit (IC) 15. Electronic device 10 can be a mobiletelephone, wireless local area network device, cable modem, Bluetoothcompatible device, or other communication device, a personal computer,server, printer, router or other computer, computer peripheral orcomputer networking device, a television, set-top box, game console,game, personal audio player or other consumer electronic device or anyother type of electronic device.

In accordance with the present invention the inductively coupled IC 15includes one or more coils or other inductive elements that are used tocouple integrated circuit dies within the integrated circuit packageand/or to couple the inductively coupled IC 15 to other inductivelycoupled ICs that are positioned in proximal location to each other.These coils operate as a transformer to generate electrical signals thatare based on the magnetic flux generated by the other coil or coils. Inthis fashion, signaling between integrated circuits and/or integratedcircuit dies can be accomplished inductively via magnetic fieldvariations. The use of inductive coupling reduces or eliminates the needfor direct electrical connections such as bonding wires, pins or padsand associated drivers and buffers and/or can substantially reduce thepower consumption of the inductively coupled IC 15.

Various functions and features of inductively coupled IC 15 aredescribed in conjunction with FIGS. 2-76.

FIG. 2 is a schematic block diagram of an embodiment of integratedcircuits 20 and 24 in accordance with the present invention. Inparticular, integrated circuits 20 and 24 are each examples ofinductively coupled IC 15. IC 20 includes a circuit 11 and IC 24includes a circuit 12 that perform functions relating to the operationof an electronic device, such as electronic device 10. IC 20 includesinductive interface 22 and IC 24 includes inductive interface 26. Theinductive interfaces 22 and 26 are aligned to magnetically communicatesignals between the circuit 11 and the circuit 12. These signals can bedigital signals, analog signals and or discrete time signals thatcontain data, clock signals, operational instructions, controlinformation or other signaling that are communicated between thecircuits 11 and 12 to, for instance, effectuate the interaction betweenthese two devices, either unidirectionally or bidirectionally. In theembodiment shown, the ICs 20 and 24 are stacked in such a fashion as toalign the inductive interfaces 22 and 26.

The ICs 20 and 24 can be bonded together to stabilize the alignmentbetween the inductive interfaces 22 and 26 and to otherwise providemechanical stability. In an embodiment of the present invention, aferromagnetic glue is used in this bonding process to facilitate thetransmission of magnetic flux between the inductive interfaces 22 and26. Such a ferromagnetic glue can include a ferromagnetic material thatis itself adhesive or bound together with an adhesive substance to forma glue that, once it is set and binds the ICS 20 and 24, conductsmagnetic flux between the inductive interfaces 22 and 26.

FIG. 3 is a schematic block diagram of an embodiment of inductiveinterfaces 22 and 26 in accordance with the present invention. WhileFIG. 2 presents an example where inductive interfaces are implemented inintegrated circuits 20 and 24. As will be discussed in conjunction withFIG. 5, the inductive interfaces can each be implemented in anintegrated circuit die, in or on a supporting substrate or partially inan integrated circuit die and partially on a substrate.

As shown, inductive interface 22 includes a coil 52 and transceiver 50and inductive interface 26 includes coil 54 and transceiver 56. Coils 52and 54 are aligned to magnetically communicate signals between thecircuit 13 and the circuit 14. In particular, these coils can include anumber of turns such as 1-5 turns or more of metal that are implementedon one or more metal layers of a corresponding IC die, of a supportingsubstrate or the IC die and substrate. In an embodiment of the presentinvention, the coils are similarly sized or sized with substantially thesame dimensions to facilitate their alignment and to facilitate theinductive coupling between the two coils. In particular, these coils canbe implemented in their corresponding IC die and/or substrate so thatthese coils can be axially and/or planarly aligned.

In operation, outbound signals 66 from circuit 13, such as circuit 11,are converted to radio frequency signals or other signals viatransceiver 50 that excite the coil 52 to generate magnetic flux that isrecovered by coil 54 and converted to inbound signals 69 to circuit 14,such as circuit 12. Similarly, outbound signals 68 from circuit 14 areconverted to radio frequency signals or other signals via transceiver 56that excite the coil 54 to generate magnetic flux that is recovered bycoil 52 and converted to inbound signals 67 to circuit 13.

In an embodiment of the present invention the transceivers 50 and 56excite the coils with frequencies ranging from 200 MHz to 13.1 GHzdepending on the implementation, however greater or lesser frequenciescould likewise be used. It should be recognized that separatefrequencies can be used for each direction of communication to allow thecontemporaneous bidirectional transmission of signals. While inductiveinterfaces 22 and 26 are shown with transceivers 50 and 56, thesetransceivers are optional. For instance, high frequency clock signalscan be included in outbound signals 66 and 68 without up-conversion toradio frequencies and with only optionally amplification or using otherdrivers, buffers that generate inductive signaling based on outboundsignals 66 and 68 and other receivers that generate inbound signals 67and 69 in response thereto.

FIG. 4 presents a schematic block diagram representation of anintegrated circuit 16 in accordance with an embodiment of the presentinvention. In this example, integrated circuit includes integratedcircuit dies 21 and 23 that are stacked on a supporting substrate 95. Asin the embodiment of FIG. 2, inductive interfaces 22 and 26 are stackedand aligned to magnetically communicate signals between the circuit 11and the circuit 12. Similarly to the embodiment of FIG. 2, the IC dies21 and 23 can be bonded together, using a ferromagnetic glue orotherwise, provide magnetic communication between the inductiveinterfaces 22 and 26 and to stabilize their alignment and to otherwiseprovide mechanical stability.

FIG. 5 presents a schematic block diagram representation of anintegrated circuit package 17 in accordance with an embodiment of thepresent invention. An integrated circuit package 17 is shown thatincludes a stacked multi-substrate configuration. In this embodiment,inductive interface 22 can be implemented in or on supporting substrate95′, in IC die 21′ or partially in both. Similarly, inductive interface26 can be implemented in or on supporting substrate 95″, in IC die 23′or partially in both. For instance, a coil, such as coil 52 or 54 caninclude multiple turns that are implemented with multiple metal layersthat include layers of both the substrate (95′ or 95″) and the IC die12′ or 23′. The coil 52 or 54 can be implemented entirely within theintegrated circuit die 21′ or 23′ and or entirely within the substrate95′ or 95″. The transceiver 50 or 56, if included, can be implementedentirely in within IC die 21′ or 23′ or at least partially within thesubstrate 95′ or 95″.

FIG. 6 is a top view of a coil 330 in accordance with the presentinvention. In particular a top view of coil 330, such as coil 52 and/orcoil 54 is shown as included in a portion of an inductively coupled IC15. As shown, the first turns 332 includes metal bridges 334 and 336 tocouple various sections of the winding together. The first turn is ondielectric layer 338, while the metal bridges 334 and 336 are on a lowerdielectric layer, which enables the first turns to maintain theirsymmetry. Optional removed dielectric sections 333 and 335 are shownthat provides greater magnetic coupling to the second turns that arebelow. The removed dielectric sections 333 and 335 can be removed usinga microelectromechanical systems (MEMS) technology such as dry etching,wet etching, electro-discharge machining, or using other integratedcircuit fabrication techniques. The remaining elements of the coil 330can be created by etching, depositing, and/or any other method forfabricating components on an integrated circuit.

FIG. 7 is a side view of a coil 330 in accordance with the presentinvention. As shown, dielectric layer 338 supports the first turns 332.A lower layer, dielectric layer 348, supports metal bridges 334 and 336.Utilizing conventional integrated circuit technologies, the metalbridges 334 and 336 are coupled to the corresponding portions of thefirst turns 332. As further shown, dielectric layer 380 supports thesecond turns 370 while dielectric layer 376 supports the metal bridges372 and 374. The first turns 332 and the second turns 370 are coupledtogether by via 337. As discussed above, removed dielectric section 335removes portions of both dielectric layers 338 and 348 to improve themagnetic coupling between the first turns 332 and second turns 370.

FIG. 8 is a bottom view of a coil 330 in accordance with the presentinvention. As shown, the second turn 370 on dielectric layer 376 and themetal bridges 372 and 374 couple the winding of the second turnstogether. The second turns have a symmetrical pattern and is similar tothe winding of the first turns 332. As one of average skill in the artwill appreciate, the first and second turns may include more or lessturns, and additional turns may also be disposed on additionaldielectric layers.

It should be noted that while FIGS. 6-8 present a particularconfiguration of an on-chip coil, other on-chip coil configurations canlikewise be employed with the broad scope of the present invention. Asdiscussed in conjunction with FIG. 3, such a coil 330 can be implementedwith a fewer or greater number of turns that is shown, on an integratedcircuit die, a substrate or partially on both. In a particularconfiguration the on-chip coil can be implemented on a substrate arounda die or a stack of dies that contain the remaining components of thecorresponding inductive interface 22 or 26, along the periphery of anintegrated circuit die or in other configurations.

FIG. 9 is a schematic block diagram of an embodiment of RF transceiver135 in accordance with the present invention. The RF transceiver 135,such as transceiver 50 or 56, includes an RF transmitter 139, and an RFreceiver 137. The RF receiver 137 includes a RF front end 140, a downconversion module 142 and a receiver processing module 144. The RFtransmitter 139 includes a transmitter processing module 146, an upconversion module 148, and a radio transmitter front-end 150.

As shown, the receiver and transmitter are each coupled to coil 171 anda diplexer (duplexer), that couples the transmit signal 155 to the coil171 to produce outbound magnetic signal 170 and inbound magnetic signal152 received by the coil 171 to produce received signal 153.Alternatively, a transmit/receive switch can be used in place ofdiplexer 177. While a single coil 171 is represented, the receiver andtransmitter may share a multiple coil structure that includes two ormore coils.

In operation, the transmitter receives outbound signals 162 via thetransmitter processing module 146. The transmitter processing module 146processes the outbound signals 162 optionally in accordance with amultiple access protocol, data protocol or other protocol to producebaseband or low intermediate frequency (IF) transmit (TX) signals 164that contain outbound signals 162. The baseband or low IF TX signals 164may be digital baseband signals (e.g., have a zero IF) or digital low IFsignals, where the low IF typically will be in a frequency range of onehundred kilohertz to a few megahertz. Note that the processing performedby the transmitter processing module 146 can include, but is not limitedto, scrambling, encoding, puncturing, mapping, modulation, and/ordigital baseband to IF conversion.

The up conversion module 148 can include a digital-to-analog conversion(DAC) module when baseband or low IF TX signals 164 are digital signals,a filtering and/or gain module, and a mixing section. The filteringand/or gain module filters and/or adjusts the gain of the analog signalsprior to providing it to the mixing section. The mixing section convertsthe analog baseband or low IF signals into up-converted signals 166based on a transmitter local oscillation.

The radio transmitter front end 150 includes a power amplifier and mayalso include a transmit filter module. The power amplifier amplifies theup-converted signals 166 to produce outbound magnetic signals 170, whichmay be filtered by the transmitter filter module, if included. Theantenna structure transmits the outbound magnetic signals 170 to anotherIC or IC die or optionally to a remote device.

The receiver receives inbound magnetic signal 152 via the coil 171 thatoperates to process the inbound magnetic signal 152 into received signal153 for the receiver front-end 140. The down conversion module 142includes a mixing section, an optionally analog to digital conversion(ADC) module when the receiver processing module operates in the digitaldomain, and may also include a filtering and/or gain module. The mixingsection converts the desired RF signal 154 into a down converted signal156 that is based on a receiver local oscillation 158, such as an analogbaseband or low IF signal. The ADC module converts the analog basebandor low IF signal into a digital baseband or low IF signal. The filteringand/or gain module high pass and/or low pass filters the digitalbaseband or low IF signal to produce a baseband or low IF signal 156that includes an inbound symbol stream. Note that the ordering of theADC module and filtering and/or gain module may be switched, such thatthe filtering and/or gain module is an analog module.

The receiver processing module 144 processes the baseband or low IFsignal 156 in accordance with an optional multiple access protocol orother protocol to produce inbound signals 160. The processing performedby the receiver processing module 144 can include, but is not limitedto, digital intermediate frequency to baseband conversion, demodulation,demapping, depuncturing, decoding, and/or descrambling.

In an embodiment of the present invention, receiver processing module144 and transmitter processing module 146 can be implemented via use ofa microprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on operational instructions. Theassociated memory may be a single memory device or a plurality of memorydevices that are either on-chip or off-chip. Such a memory device may bea read-only memory, random access memory, volatile memory, non-volatilememory, static memory, dynamic memory, flash memory, and/or any devicethat stores digital information. Note that when the these processingdevices implement one or more of their functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, theassociated memory storing the corresponding operational instructions forthis circuitry is embedded with the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.

While the processing module 144 and transmitter processing module 146are shown separately, it should be understood that these elements couldbe implemented separately, together through the operation of one or moreshared processing devices or in combination of separate and sharedprocessing.

FIG. 10 presents a schematic block diagram representation of anintegrated circuit 18 in accordance with an embodiment of the presentinvention. In this configuration, integrated circuit 18 includesintegrated circuit dies 30 and 34 having inductive interfaces 22 and 26.Supporting substrate 94 supports integrated circuit dies 30 and 34 andfurther includes a magnetic communication path 98 that is aligned withthe inductive interface 22 and 26 to magnetically communicate signalsbetween circuits that are included on the IC dies 30 and 34. Inparticular, magnetic communication path 98 operates to couple magneticsignals generated by inductive interface 22 to inductive interface 26and thus allows IC dies 30 and 34 to communicate in a similar fashion toIC dies 21 and 23 and/or ICs 20 and 24.

Further functions and features of the magnetic communication path 98will be discussed in conjunction with FIGS. 11-17 that follow.

FIG. 11 is a schematic block diagram of an embodiment of integratedcircuit dies 30 and 34 in accordance with the present invention. Asdiscussed in conjunction with FIG. 3, inductive interfaces 22 and 26include coils 52, 54. In this configuration however, coils 52 and 54 arealigned to bidirectionally or unidirectionally communicate via themagnetic communication path 98. In an embodiment of the presentinvention, the IC dies 30 and 34 are bonded to supporting substrate 94using a ferromagnetic glue or other bonding technique that supports thetransfer of magnetic flux from coils 52 and 54 to the magneticcommunication path 98.

In operation, outbound signals 66 from circuit 13 are converted to radiofrequency signals or other signals via transceiver 50 or other driverthat excite the coil 52 to generate magnetic flux that is received bymagnetic communication path 98 and that generates a correspondingmagnetic flux on coil 54. Coil 54 and transceiver 56 or other receiveror amplifier converts this magnetic flux to inbound signals 69 forcircuit 14. Similarly, outbound signals 68 from circuit 14 are convertedto radio frequency signals or other signals via transceiver 56 or otherbuffer that excite the coil 54 to generate magnetic flux that isreceived by magnetic communication path 98 and that generates acorresponding magnetic flux on coil 52. Coil 52 and transceiver 50 orother receiver or amplifier converts this magnetic flux to inboundsignals 67 for circuit 13.

While integrated circuit dies 30 and 34 are shown as both being on thesame side of the supporting substrate, in an another configuration, theIC dies 30 and 34 can be bonded to opposite sides of the supportingsubstrate, such as in the flip chip configuration that is shown inconjunction with FIGS. 14 and 15. In this configuration, the magneticcommunication path 98 is provided to conduct magnetic flux through thesupporting substrate 94 to opposing sides of the supporting substrate atpoints that align with the coils of inductive interfaces 22 and 26.

FIG. 12 is a schematic block diagram of magnetic communication path 98in accordance with an embodiment the present invention. In particular,magnetic communication path 98 can include two coils 58 and 59 that arecoupled together and that are aligned with the coils 52 and 54 of theinductive interfaces 22 and 26. In operation, the pairs of coils (52,58)and (59,54) coils are similarly sized or sized with substantially thesame dimensions to facilitate their alignment and to facilitate theinductive coupling between the coil pairs. In particular, these coilscan be implemented in their corresponding IC die or substrate so thatthese coils can be axially and/or planarly aligned. Magnetic flux fromcoil 52 is received by coil 58 and converted to an electrical signalthat generates a corresponding electrical flux via coil 59 that isreceived by coil 54. Similarly, magnetic flux from coil 54 is receivedby coil 59 and converted to an electrical signal that generates acorresponding electrical flux via coil 58 that is received by coil 52.

FIG. 13 is a schematic block diagram of magnetic communication path 98′in accordance with another embodiment the present invention. Inparticular, magnetic communication path 98′ operates in place ofmagnetic communication path 98, yet with magnetically conductivematerial 96 provided in place of coils 58 and 59. In particular, thesubstrate of an IC such as IC 18, is provided with one or more ferriterods, a powdered iron structure, another ferromagnetic material or othermagnetically conductive material that conducts magnetic flux from coil52 to coil 54 and from coil 54 to coil 52. In operation, the coils 52and 54 are aligned to the magnetically conductive path 98′ to facilitatethe inductive coupling between the coils 52 and 54. Magnetic flux fromcoil 52 is received by coil 54. Similarly, magnetic flux from coil 54 isreceived by coil 52.

FIG. 14 is a side view of a pictorial representation of an integratedcircuit package in accordance with the present invention. RF IC 325 issimilar to IC 18 however, as discussed in conjunction with FIG. 11, aflip-chip configuration is shown. In particular, with integrated circuitdie 302, such as IC die 30, is bonded to the top of substrate 306, whileintegrated circuit die 304 is bonded to the bottom of the substrate 36.This figure is not drawn to scale. In particular, the RF IC 325 isintegrated in a package having a plurality of bonding pads 308 toconnect the RF IC 325 to a circuit board.

Substrate 306 includes a magnetic communication path, such as magneticcommunication path 98 or 98′ to conduct magnetic flux through thesupporting substrate 306 to opposing sides of the supporting substrateat points that align with the inductive interfaces of IC dies 302 and304. The IC dies 302 and 304 are stacked and inductive coupling isemployed to connect these two circuits and minimize the number ofbonding pads, (balls) out to the package. IC die 302 and IC die 304 canbe coupled to respective ones of the bonding pads 308 via bonding wiresor other connections. The positioning of the IC die 304 on the bottom ofthe package in a flip chip configuration allows good heat dissipation ofthe IC die 304 to a circuit board.

FIG. 15 is a bottom view of a pictorial representation of an integratedcircuit package in accordance with the present invention. As shown, thebonding pads (balls) 308 are arrayed in an area of the bottom of theintegrated circuit with an open center portion 310 and wherein the ICdie 304 is integrated in the open center portion. While a particularpattern and number of bonding pads 308 are shown, a greater or lessernumber of bonding pads can likewise be employed with alternativeconfigurations within the broad scope of the present invention.

FIG. 16 is a pictorial representation of integrated circuit 19 inaccordance with an embodiment the present invention. In particular, aportion of integrated circuit 19 is shown with die 70, such as IC die 30or 34 bonded to package substrate 72, such as supporting substrate 94. Across section is shown that identifies a region of die 70 that includesa portion of coil 74, such as coil 52 or 54. Further, this cross sectionalso identifies a region of package substrate 72 that includes a portionof magnetic communication path 96, such as magnetic communication path98 or 98′. As shown by the regions of the coil 74 and magneticcommunication path 96 that are included in this cross section, theseportions are aligned to facilitate the conduction of magnetic fluxtherebetween.

FIG. 17 is a pictorial representation of integrated circuit 51 inaccordance with an embodiment the present invention. In particular,while FIGS. 10-16 have focused on integrated circuits having asupporting substrate that includes a magnetic communication path thatfacilitates the communication between two IC dies with inductiveinterfaces, IC 51 presents a top view, not to scale, of an integratedcircuit that includes a magnetic communication path 97, such as magneticcommunication path 96, 98 or 98′, that couples eight integrated circuitdies 49. While each of these eight IC dies 49 are referred to by commonreference numerals, they can be implemented each with different circuitsor two or more circuits that are the same. Each of the integratedcircuit dies 49 is shown having a coil in the region 47 that is alignedwith a portion of the magnetic communication path 97 that lies in thesupporting substrate that is beneath the integrated circuit dies 49.While not expressly shown, one or more IC dies could likewise bedisposed below the substrate with coils in alignment with the magneticcommunication path 97. In this fashion, magnetic communication path 97couples inductive interfaces, such as inductive interfaces 22 or 26 of aplurality of IC dies above the supporting substrate and also below thesupporting substrate. In an embodiment of the present invention, each ofthe IC dies 49 include inductive interfaces, such as inductiveinterfaces 22 or 26 that implement a multiple access protocol as part ofa transceiver, driver, receiver, etc.

While RF ICs 16, 17, 18, 19, 51 and 325 provide several possibleimplementations of inductively coupled IC 15, other circuits includingother integrated circuit packages can be implemented including otherstacked, in-line, surface mount and flip chip configurations.

FIG. 18 is a schematic block diagram of an embodiment of integratedcircuits 40 and 44 in accordance with the present invention. Inparticular ICs 40 and 44 include inductive interfaces 22 and 26 thatoperate as previously described. In addition, ICs 40 and 44 furtherinclude millimeter wave interfaces 46 and 48 that communicate signalstherebetween via millimeter wave communication path 42. In this fashion,signaling can be transferred between ICS 40 and 44 via two interfaces.For instance, signals can be segregated into high frequency and lowfrequency signals or high data rate and low data rate signals based onthe implementation of the inductive and millimeter wave communicationsbetween the ICs 40 and 44 and transmitted via one or the other of thesetwo communication media. Further, signals can be segregated fortransmission into shared medium and dedicated medium signals when eitherthe inductive interfaces 22, 26 or the millimeter wave interfaces 46, 48share their communication medium with other devices such as otherintegrated circuits, other integrated circuit dies and/or remotedevices. In addition, the magnetic and millimeter wave communicationpaths between ICs 40 and 44 can be used in the implementation of an RFbus interface between two or more integrated circuits that that includestwo or more communication paths.

FIG. 19 is another schematic block diagram of an embodiment ofintegrated circuits 40 and 44 in accordance with the present invention.In particular, ICs 40 and 44 include inductive interfaces 22 and 26 thatoperate as described in conjunction with FIG. 3. While FIGS. 18 and 19present examples where inductive interfaces 22 and 24 are implemented inintegrated circuits 40 and 44, as shown in other embodiments, inductiveinterfaces 22 and 26 can each be implemented in an integrated circuitdie, in or on a supporting substrate or partially in an integratedcircuit die and partially on a substrate. Further, while FIGS. 18 and 19present examples where millimeter wave interfaces 46 and 48 areimplemented in integrated circuits 40 and 44, as will be discussed inconjunction with FIGS. 21 and 22, the inductive interfaces can each beimplemented in an integrated circuit die, or further in or on asupporting substrate or partially in an integrated circuit die andpartially on a substrate.

As shown, millimeter wave interface 46 includes an antenna 52′ andtransceiver 50′ and millimeter wave interface 48 includes antenna 54′and transceiver 56′. Antennas 52′ and 54′ are aligned toelectromagnetically communicate signals between the circuit 13 and thecircuit 14. In particular, these antennas can include one or moreantenna elements that are implemented on one or more metal layers of acorresponding IC die, of a supporting substrate or the IC die andsubstrate. In an embodiment of the present invention, the antennas aresimilarly sized and aligned to facilitate the transfer ofelectromagnetic signals between the two antennas via a wave guide,through a dielectric material, substrate, free space or other portion ofICs 40 and 44. In particular, these antennas can be implemented in theircorresponding IC die and/or substrate to generate electromagneticemissions that are either substantially omni-directional on one or moreplanes or transmission or optionally directed toward the other antenna.

In operation, outbound signals 66′ from circuit 13, such as circuit 11,are converted to radio frequency signals or other signals viatransceiver 50′ that excite the antenna 52′ to generate anelectromagnetic field that is recovered by antenna 54′ and converted toinbound signals 69′ to circuit 14, such as circuit 12. Similarly,outbound signals 68′ from circuit 14 are converted to radio frequencysignals or other signals via transceiver 56′ that excite the antenna 54′to generate an electromagnetic field that is recovered by coil 52′ andconverted to inbound signals 67′ to circuit 13.

In an embodiment of the present invention the transceivers 50 and 56operate in a millimeter wave band such as a 60 GHz band, however greateror lesser frequencies could likewise be used. It should be recognizedthat separate frequencies or frequency channels can be used for eachdirection of communication to allow the contemporaneous bidirectionaltransmission of signals.

FIG. 20 is a schematic block diagram of an embodiment of integratedcircuits 40, 41 and 43 in accordance with the present invention. Inparticular, a multiple IC structure is shown with ICs 40, 41 and 43 thatincludes a plurality of ICs (40, 43) communicating via inductiveinterfaces and a plurality of ICs (40, 41) communication via millimeterwave interfaces. It should be noted that this stacked structure is notrequired and further integrated circuits can be implemented in thisfashion, with one, several or all of the ICs including correspondingmillimeter wave interfaces and one, several or all of the ICs includinginductive interfaces as part of a single or dual RF bus structure or tootherwise facilitate communication between these ICs. In this particularstructure IC 40 includes both inductive interface 22 and millimeter waveinterface 48 and can be used to transfer signals between IC 41 and IC 43by converting magnetic/inductive communication from IC 43 to millimeterwave communications received by IC 41, and by converting millimeter wavecommunications from IC 41 to magnetic/inductive communications receivedby IC 43.

In an embodiment of the present invention, one or more of the millimeterwave interfaces 46 or 48 can further send and receive signals with anexternal device such as a remote communication device or other devicethat includes a millimeter wave transceiver.

FIG. 21 is a pictorial representation of integrated circuit 71 inaccordance with an embodiment the present invention. IC 71 includes aplurality of integrated circuit dies 51, 53 and 55. In particular,integrated circuit dies 51 and 55 have corresponding millimeter waveinterfaces 46 and 48 for communication with each other via millimeterwave communication path 42 or with one or more remote devices such asother ICs, communication devices or other devices that include amillimeter wave transceiver. IC dies 53 and 55 have inductive interfaces22 and 26 for communication as previously described.

It should be noted that further integrated circuits can be implementedin this fashion, but in different configurations including additional ICdies, with one, several or all of the IC dies including correspondingmillimeter wave interfaces and one, several or all of the IC diesincluding inductive interfaces as part of a single or dual RF busstructure or to otherwise facilitate communication between these ICdies. In this particular structure IC die 55 includes both inductiveinterface 26 and millimeter wave interface 48 and can be used totransfer signals between IC dies 51 and 53 by convertingmagnetic/inductive communication from IC die 53 to millimeter wavecommunications received by IC die 51, and by converting millimeter wavecommunications from IC die 51 to magnetic/inductive communicationsreceived by IC die 53.

FIG. 22 is a pictorial representation of integrated circuit 73 inaccordance with an embodiment the present invention. Integrated circuit73 includes IC dies 54 and 50 that include corresponding circuits andmillimeter wave interfaces 46 and 48 that operate as previouslydescribed. In this configuration, IC dies 50 and 54 include inductiveinterfaces 22 and 26 that communication via magnetic communication path97, 98 or 98′ that is included in supporting substrate 94 as previouslydescribed.

It should be noted that further integrated circuits can be implementedin this fashion, but in different configurations including additional ICdies, with one, several or all of the IC dies including correspondingmillimeter wave interfaces and one, several or all of the IC diesincluding inductive interfaces as part of a single or dual RF busstructure or to otherwise facilitate communication between these ICdies.

FIG. 23 is a pictorial and block diagram representation of electronicdevice 80 in accordance with an embodiment the present invention. Inparticular Electronic device 80 includes an inductively coupled IC suchas IC 40, 71 or 73 that can communication with remote devices via amillimeter wave transceiver such as millimeter wave transceiver 50′ or56′. In particular personal computer 82, RFID card 87, camera 83,printer 84, personal digital assistant 85 and mobile communicationdevice 86 present examples of devices that can include a millimeter wavetransceiver to communicate with electronic device 80 in accordance witha standard or other wireless protocol. Electronic device 80, likeelectronic device 10, can itself be a mobile telephone, wireless localarea network device, cable modem, Bluetooth compatible device, or othercommunication device, a personal computer, server, printer, router orother computer, computer peripheral or computer networking device, atelevision, set-top box, game console, game, personal audio player orother consumer electronic device or any other type of electronic device.

FIG. 24 is a schematic block diagram of an embodiment of RF transceiver1035 in accordance with the present invention. In particular, the RFtransceiver 1035, such as millimeter wave transceiver 50′ or 56′includes an RF transmitter 1039, and an RF receiver 1037. The RFreceiver 1037 includes a RF front end 1040, a down conversion module1042 and a receiver processing module 1044. The RF transmitter 1039includes a transmitter processing module 1046, an up conversion module1048, and a radio transmitter front-end 1050.

As shown, the receiver and transmitter are each coupled to an antennathrough an antenna interface 1071 and a diplexer (duplexer) 1077, thatcouples the transmit signal 1055 to the antenna to produce outbound RFsignal 1070 and couples inbound signal 1052 to produce received signal1053. Alternatively, a transmit/receive switch can be used in place ofdiplexer 1077. While a single antenna is represented, the receiver andtransmitter may share a multiple antenna structure that includes two ormore antennas. In another embodiment, the receiver and transmitter mayshare a multiple input multiple output (MIMO) antenna structure,diversity antenna structure, phased array or other controllable antennastructure that includes a plurality of antennas. Each of these antennasmay be fixed, programmable, and antenna array or other antennaconfiguration. Also, the antenna structure of the wireless transceivermay depend on the particular standard(s) to which the wirelesstransceiver is compliant and the applications thereof.

In operation, the transmitter receives outbound signals 1062 from acircuit such as outbound signals 66′ or 68′ via the transmitterprocessing module 1046. The transmitter processing module 1046 processesthe outbound signals 1062, such as outbound signals 67′ or 69′ in amillimeter wave protocol to produce baseband or low intermediatefrequency (IF) transmit (TX) signals 1064 that contain outbound signals1062. The baseband or low IF TX signals 1064 may be digital or analogbaseband signals (e.g., have a zero IF) or digital low IF signals, wherethe low IF typically will be in a frequency range of one hundredkilohertz to a few megahertz. Note that the processing performed by thetransmitter processing module 1046 can include, but is not limited to,scrambling, encoding, puncturing, mapping, modulation, and/or digitalbaseband to IF conversion.

The up conversion module 1048 includes an optional digital-to-analogconversion (DAC) module, a filtering and/or gain module, and a mixingsection. The DAC module, if included, converts the baseband or low IF TXsignals 1064 from the digital domain to the analog domain. The filteringand/or gain module filters and/or adjusts the gain of the analog signalsprior to providing it to the mixing section. The mixing section convertsthe analog baseband or low IF signals into up-converted signals 1066based on a transmitter local oscillation.

The radio transmitter front end 1050 includes a power amplifier and mayalso include a transmit filter module. The power amplifier amplifies theup-converted signals 1066 to produce outbound RF signals 1070, which maybe filtered by the transmitter filter module, if included. The antennastructure transmits the outbound RF signals 1070 to a targeted devicesuch as an IC or IC die, RF tag, base station, an access point and/oranother wireless communication device via an antenna interface 1071coupled to an antenna that provides impedance matching and optionalbandpass filtration.

The receiver receives inbound RF signals 1052 via the antenna andantenna interface 1071 that operates to process the inbound RF signal1052 into received signal 1053 for the receiver front-end 1040. Ingeneral, antenna interface 1071 provides impedance matching of antennato the RF front-end 1040, optional bandpass filtration of the inbound RFsignal 1052.

The down conversion module 1042 includes a mixing section, an optionalanalog to digital conversion (ADC) module, and may also include afiltering and/or gain module. The mixing section converts the desired RFsignal 1054 into a down converted signal 1056 that is based on areceiver local oscillation, such as an analog baseband or low IF signal.The ADC module converts the analog baseband or low IF signal into adigital baseband or low IF signal. The filtering and/or gain module highpass and/or low pass filters the digital baseband or low IF signal toproduce a baseband or low IF signal 1056. Note that the ordering of theADC module and filtering and/or gain module may be switched, such thatthe filtering and/or gain module is an analog module.

The receiver processing module 1044 processes the baseband or low IFsignal 1056 in accordance with a millimeter wave communication protocolto produce inbound signals 1060, such as inbound signals 67′ or 69′. Theprocessing performed by the receiver processing module 1044 can include,but is not limited to, digital intermediate frequency to basebandconversion, demodulation, demapping, depuncturing, decoding, and/ordescrambling.

In an embodiment of the present invention, receiver processing module1044, and transmitter processing module 1406 can be implemented via useof a microprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on operational instructions. Theassociated memory may be a single memory device or a plurality of memorydevices. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, and/or any device that stores digital information.Note that when the these processing devices implement one or more oftheir functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the associated memory storing thecorresponding operational instructions for this circuitry is embeddedwith the circuitry comprising the state machine, analog circuitry,digital circuitry, and/or logic circuitry.

FIG. 25 is schematic block diagram of an embodiment of integratedcircuits 60 and 24 in accordance with the present invention. IC 24includes a circuit and an inductive interface 26. IC 60 includes acircuit and an inductive interface 62 that operates in a similar fashionto inductive interface 22 to communicate with inductive interface 26 andis further operable to engage in near field communications, such as RFIDcommunications with a remote device 65. In particular, the coil, such ascoil 52, used to communicate with inductive interface 26 can be furtheremployed as a near field coil to respond to near field communicationwith external devices such as an RFID tag or RFID terminal or other nearfield communications device to send and/or receive signals via thesenear field communications.

Further functions and features of inductive interface 62 are presentedin conjunction with FIG. 27.

FIG. 26 is a pictorial representation of integrated circuit 75 inaccordance with an embodiment the present invention. IC 75 includes anIC die 34 that includes a circuit and an inductive interface 26. IC die64 includes a circuit and an inductive interface 62 that operates in asimilar fashion to inductive interface 22 to communicate with inductiveinterface 26 via magnetic communication path 97, 98 or 98′ and isfurther operable to engage in near field communications, such as RFIDcommunications with a remote device 65. In particular, the coil, such ascoil 52, used to communicate with inductive interface 26 can be furtheremployed as a near field coil to respond to near field communicationwith external devices such as an RFID tag or RFID terminal or other nearfield communications device to send and/or receive signals via thesenear field communications.

Further functions and features of inductive interface 62 are presentedin conjunction with FIG. 27.

FIG. 27 is a schematic block diagram of an embodiment of aninductive/RFID interface in accordance with the present invention.Inductive/RFID interface 575, such as inductive/RFID interface 62,includes an antenna structure 452, such as coil 52, an optional powerrecovery circuit 450, a data recovery module 456, a processing module458, an oscillation module 454, and a transmitting circuit 460. Theprocessing module 458 may be a single processing device or a pluralityof processing devices. Such a processing device may be a microprocessor,micro-controller, digital signal processor, microcomputer, centralprocessing unit, field programmable gate array, programmable logicdevice, state machine, logic circuitry, analog circuitry, digitalcircuitry, and/or any device that manipulates signals (analog and/ordigital) based on hard coding of the circuitry and/or operationalinstructions. The processing module may have an associated memory and/ormemory element, which may be a single memory device, a plurality ofmemory devices, and/or embedded circuitry of the processing module. Sucha memory device may be a read-only memory, random access memory,volatile memory, non-volatile memory, static memory, dynamic memory,flash memory, cache memory, and/or any device that stores digitalinformation. Note that when the processing module implements one or moreof its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory and/or memory elementstoring the corresponding operational instructions may be embeddedwithin, or external to, the circuitry comprising the state machine,analog circuitry, digital circuitry, and/or logic circuitry.

In operation, the antenna structure 452 can be sized for operation forfrequencies used in magnetic communication with other ICs and other ICdies and further for near field communication with remote devices 65. Inan embodiment of the present invention, one frequency band is used forboth types of communications and alternative multiple access techniquesare used to avoid interference and to separate signaling using ininductive coupling and signaling used in near field communications. Inanother embodiment of the present invention, separate frequency bandsare used for inductive coupling and near-field communications and theantenna structure is designed for operation in both frequency bands.

Antenna structure 452 receives an RF signal 462 either via inductivecoupling with an inductive interface of another IC die or IC or via nearfield communications with a remote device. The RF signal 462 may be acontinuous wave signal or other signal. The antenna structure 452provides the received RF signal 462 to the optional power recoverycircuit 450 (when included) and the data recovery circuit 456.

When included. the power recovery circuit 450 converts the RF signal 462into a supply voltage (Vdd) 464. In one embodiment, the power recoverycircuit 450 includes a rectifying module, which may be an active cellrectifier or a charge pump rectifier, and a tuning module. The tuningmodule tunes the rectifying module in accordance with the RF signal. Inother words, the tuning module tunes the frequency response of therectifying module based on the frequency of the RF signal such that thefrequency response of the power recovery circuit 450 is optimized forthe RF signal 462. The rectifying module, having been tuned, rectifiesthe RF signal 462 and stores the rectified RF signal in a capacitor toproduce the supply voltage 464, which is used to power the data recoverymodule 456, the processing module 458, the oscillation module 454, andthe transmitting circuit 460. When the optional power recovery circuit450 is not included, the supply voltage Vdd is provided by aconventional or alternative power supply.

The oscillation module 454 produces an oscillation 466 having afrequency approximately equal to a carrier frequency of the RF signal462. The oscillation module 454 provides the oscillation 466 to the datarecovery module 456 and may also provide the oscillation to theprocessing module 458.

The data recovery module 456 is clocked via the oscillation 466 torecover data 468 from the RF signal 462 including signals and other datareceived via near field communications or from another inductiveinterface. For example, the RF signal 462 includes bi-phase encoded datathat has the state of the encoded signal change at the bit boundariesand, within the bit boundaries, a constant state may represent a logicone and a toggle state may represent a logic zero. In this example, thedata recovery module 456 recovers the bi-phase encoded data as therecovered data 468 and provides it to the processing module 458. Inanother example, the data recovery module 456 may decode the recoveredbi-phase encoded data to produce the recovered data 468.

The processing module 468 processes the recovered data 468 andoptionally provides separate feeds of the recovered data 468representing data resulting from near field communications and dataresulting from magnetic communications with other inductive interfaces,to a circuit, such as circuit 11, 12, 13 or 14. In an embodiment of thepresent invention, the processing module operates in accordance with amultiple access protocol that provides either contemporaneous or serialcommunication between the two communication paths. Either communicationpath may be implemented as part of an single or multiple RF busstructure having further functions and features that will be describedin greater detail in conjunction with FIGS. 28-61.

When indicated within the recovered data 468 or otherwise in response tosignals or data from a circuit such as circuit 11, 12, 13 or 14,outbound data 470 is provided to transmitting circuit 460. Thetransmitting circuit 460, which may be a transistor or other transmittercircuit provides the outbound data 470 to the antenna structure 452 fortransmission as an outbound signal 472.

FIG. 28 is a schematic block diagram of an embodiment of an RF bus thatinterfaces a plurality of integrated circuits and or integrated circuitdies 1084, and 1086, and includes an RF bus controller 1088. Forexample, the ICs 1084, 1086, can be any of the ICs or IC dies thatinclude an inductive interface such as inductive interface 22, 26, or62, and/or that include a millimeter wave interface such as millimeterwave interfaces 46 and 48. ICs 1084 and 1086 each include a circuit suchas a microprocessor, microcontroller, digital signal processor,programmable logic circuit, memory, application specific integratedcircuit (ASIC), analog to digital converter (ADC), digital to analogconverter (DAC), digital logic circuitry, analog circuitry, graphicsprocessor, or other analog or digital circuit.

In this embodiment, IC 1084 includes a first radio frequency (RF) bustransceiver 1108 and IC 1086 includes a second RF bus transceiver 1110to support intra-device RF communications 1090 therebetween such astransceivers 52, 54, 52′ and/or 54′. The intra-device RF communications1090 may be RF data communications, RF instruction communications, RFcontrol signal communications, and/or RF input/output communicationsthat are transmitted via near-field communications, magneticcommunications and/or millimeter wave communications. For example, data,control, operational instructions, and/or input/output signals (e.g.,analog input signals, analog output signals, digital input signals,digital output signals) that are traditionally conveyed between ICs viatraces on a printed circuit board are, in millimeter wave interface 1080transmitted via the intra-device RF communications 1090. It should benoted that ICs 1084 and 1086 can include multiple RF buses that operatein different frequency bands and/or with different modes ofcommunications such as near-field communication, millimeter wavecommunication and magnetic communication. These multiple buses canoperate separately or part of a multi-bus architecture.

The intra-device RF communications 1090 may also include operatingsystem level communications and application level communications. Theoperating system level communications are communications that correspondto resource management of the millimeter wave interface 1080 loading andexecuting applications (e.g., a program or algorithm), multitasking ofapplications, protection between applications, device start-up,interfacing with a user of the millimeter wave interface 1080 etc. Theapplication level communications are communications that correspond tothe data conveyed, operational instructions conveyed, and/or controlsignals conveyed during execution of an application.

In an embodiment of the present invention the RF bus operates inaccordance with a multi-access protocol such as a time division multipleaccess protocol, a frequency division multiple access protocol, randomaccess protocol and a code division multiple access protocol. The RF buscontroller 1088 is coupled to control the intra-device RF communications1090 between the first and second RF bus transceivers 1108, 1110. The RFbus controller 1088 may be a separate IC or it may be included in one ofthe ICs 1084, 1086. In operation, the RF bus controller arbitratesaccess to the RF bus. In an embodiment of the present invention, the RFbus controller is operable to receive an RF bus access request,determine RF bus resource availability, determine when sufficient RF busresources are available, and allocate at least one RF bus resource whensufficient RF bus resources are available. Also, the RF bus controllercan optionally poll the plurality of inductive interfaces, and allocateat least one RF bus resource in response to poll. Further, the RF buscontroller can optionally receive a request to reserve at least one RFbus resource from one of the plurality of inductive interfaces, andreserve one or more RF bus resources in response to the request.

In this embodiment, the intra-device RF communications 1090 occur over afree-space RF communication path. In other words, the intra-device RFcommunications 1090 are conveyed via the air. In another embodiment, theintra-device RF communications 1090 can occur via a waveguide RFcommunication path that, for instance, may be formed in amicro-electromechanical (MEM) area of the supporting substrate. In yetanother embodiment, a dielectric layer can provide a dielectric RFcommunication path for the intra-device RF communications 1090. Furtherintra-device communications can take place vie a magnetic communicationpath such as magnetic communication path 97, 98 or 98′.

In an embodiment of present invention the RF bus controller 1088 furtherfunctions to select a communication path (the waveguide RF communicationpath, the dielectric layer RF communication path, the magneticcommunication path or the free space RF communication path) as well asthe particular communications mode (near-field, millimeter wave ormagnetic) based on at least one aspect of one of the intra-device RFcommunications. For example, high data rate and/or non-error tolerantcommunications (e.g., operating system level communications) may occurover the waveguide RF communication path, while lower data rate and/orerror tolerant communications (e.g., some portions of application levelcommunications) may occur over the free-space RF communication path. Asanother example, the aspect on which the RF communication path isselected may be user defined, operating system level defined, and/orpre-programmed into the device. As yet another example, the aspect maycorrespond to the IC initiating an intra-device RF communication and/orthe IC receiving it. As a further example, the aspect may correspond tothe number of intra-device RF communications 1090 an IC currently has inprogress.

Further functions and features of the RF bus controller 1088 will bedescribed in greater detail with reference to the figures that follow.

FIG. 29 is a schematic block diagram of an embodiment of an RF interface1080 that interfaces the ICs 1084, 1086 and includes the RF buscontroller 1088. In this embodiment, the RF bus controller 1088 includesan RF bus transceiver 1130, IC 1084 includes a circuit module 1132 andthe RF bus transceiver 1108, and IC 1086 includes a circuit module 1134and the RF bus transceiver 1110. The circuit modules 1132, 1134 may beany type of digital circuit, analog circuit, logic circuit, and/orprocessing circuit. For example, one of the circuit modules 1132, 1134may be, but is not limited to, a microprocessor, a component of amicroprocessor, cache memory, read only memory, random access memory,programmable logic, digital signal processor, logic gate, amplifier,multiplier, adder, multiplexor, etc.

In this embodiment, the inter-device RF communication 1090, RF busrequests 1122, and the RF bus grants 1124 occur within the samefrequency spectrum. To minimize interference between the obtainingaccess to the RF bus and using the RF bus for the inter-device RFcommunications 1090, the bus controller 1088 controls access to thefrequency spectrum by allocating at least one communication slot perframe to the wireless interface and allocating at least one othercommunication slot per frame for the intra-device RF communications. Thecommunication slots may be time division multiple access (TDMA) slotswithin a TDMA frame, frequency division multiple access (FDMA) slots ofan FDMA frame, and/or code division multiple access (CDMA) slots of aCDMA frame. Note that in this embodiment, frame is equivalent to apacket.

FIG. 30 is a diagram of an example of a frame of obtaining access to anRF Bus and using the RF bus by the embodiment of FIG. 26. The frame, orpacket, includes a controller inquiry field 1140, an IC response controlfield or fields 1142, a resource allocation field or fields 1144, and adata field or fields 1146. The RF bus controller uses the controllerinquiry field 1140 to determine whether one or more ICs have anup-coming need to access the RF bus. In one embodiment, the RF buscontroller 1088 addresses a single IC per frame as to whether the IC hasan up-coming need for the RF bus. In another embodiment, the RF buscontroller 1088 addresses two or more ICs as to whether they have anup-coming need for the RF bus. The RF bus controller 1088 may be use apolling mechanism to address the ICs, which indicates how and when toresponse to the polling inquiry.

The ICs 1084, 1086 respond to the RF bus controller's query in the ICresponse control field or fields 1142. In one embodiment, the ICs sharea single IC response control field using a carrier sense multiple access(CSMA) with collision avoidance technique, using pre-assigned sub-slots,using a round robin technique, using a poll-respond technique, etc. Inanother embodiment, the ICs have their own IC response control field1142. In either embodiment, the ICs 1084, 1086 response includes anindication of whether it has data to convey via the RF bus, how muchdata to convey, the nature of the data (e.g., application data,application instructions, operating system level data and/orinstructions, etc.), the target or targets of the data, a priority levelof the requestor, a priority level of the data, data integrityrequirements, and/or any other information relating to the conveyance ofthe data via the RF bus.

The RF bus controller 1088 uses the resource allocation field or fields1144 to grant access to the RF bus to one or more ICs 1084, 1086. In oneembodiment, the RF bus controller 1088 uses a single field to respond toone or more ICs. In another embodiment, the RF bus controller 1088responds to the ICs in separate resource allocation fields 1144. Ineither embodiment, the RF bus grant 1144 indicates when, how, and forhow long the IC has access to the RF bus during the one or more datafields 1146. Various embodiments of requesting and obtaining access tothe RF bus and transceiving via the RF bus will be described in greaterdetail with reference to the Figures that follow.

FIG. 31 is a schematic block diagram of another embodiment of the RFinterface 1080 that interfaces the ICs 1084, 1086 and includes the RFbus controller 1088. In this embodiment, the RF bus controller 1088includes an RF bus transceiver 1130. IC 1084 includes the circuit module132 the RF bus transceiver 1108, and an RF transceiver 1160. IC 1086includes the circuit module 1134, the RF bus transceiver 1110, and an RFtransceiver 1152.

In this embodiment, the inter-device RF communications 1090 occur in adifferent frequency spectrum than the RF bus requests 1122 and the RFbus grants 1124. As such, they can occur simultaneously with minimalinterference. In this manner, the RF bus requests 1122 and RF bus grants1124 may be communicated using a CSMA with collision avoidancetechnique, a poll-response technique, allocated time slots of a TDMAframe, allocated frequency slots of an FDMA frame, and/or allocated codeslots of a CDMA frame in one frequency spectrum or using one carrierfrequency and the inter-device RF communications 1090 may use a CSMAwith collision avoidance technique, a poll-response technique, allocatedtime slots of a TDMA frame, allocated frequency slots of an FDMA frame,and/or allocated code slots of a CDMA frame in another frequencyspectrum or using another carrier frequency.

FIG. 32 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces a plurality of integratedcircuits (ICs) 1160, 1162 and includes the RF bus controller 1088, andan RF bus 1190. Each of the ICs 1160, 1162 includes a plurality ofcircuit modules 1170-1176 and each of the circuit modules 1170-1176includes a radio frequency (RF) bus transceiver 1180-1186. The circuitmodules 1170-1176 may be any type of digital circuit, analog circuit,logic circuit, and/or processing circuit that can be implemented on anIC. For example, one of the circuit modules 1170-1176 may be, but is notlimited to, a microprocessor, a component of a microprocessor, cachememory, read only memory, random access memory, programmable logic,digital signal processor, logic gate, amplifier, multiplier, adder,multiplexer, etc.

In this embodiment, the RF bus controller 1088, which may be a separateIC or contained with one of the ICs 1160-1162, controls intra-IC RFcommunications 1192 between circuit modules 1170-1176 of different ICs1160, 1162 and controls inter-IC RF communications 1194 between circuitmodules 1170-1172 or 1174-1176 of the same IC. In this manner, at leastsome of the communication between ICs and between circuit modules of anIC is done wirelessly via the RF bus transceivers 1180-1186. Note thatthe circuit modules 1170-1172 may also be inter-coupled with one or moretraces within the IC 1160, the circuit modules 1174-1176 may also beinter-coupled with one or more traces within the IC 1162, and that IC1160 may be coupled to IC 1162 via one or more traces on a supportingsubstrate (e.g., a printed circuit board).

The intra-IC RF communications 1192 and the inter-IC RF communications1194 may be RF data communications, RF instruction communications, RFcontrol signal communications, and/or RF input/output communications.For example, data, control, operational instructions, and/orinput/output communications (e.g., analog input signals, analog outputsignals, digital input signals, digital output signals) that aretraditionally conveyed between ICs via traces on a printed circuit boardare at least partially transmitted by the RF bus transceivers 1180-1186via the RF bus 1190.

The intra-IC RF communications 1192 and/or the inter-IC RFcommunications 1194 may also include operating system levelcommunications and application level communications. The operatingsystem level communications are communications that correspond toresource management of the millimeter wave interface 1080 loading andexecuting applications (e.g., a program or algorithm), multitasking ofapplications, protection between applications, device start-up,interfacing with a user of the device, etc. The application levelcommunications are communications that correspond to the data conveyed,operational instructions conveyed, and/or control signals conveyedduring execution of an application.

The RF bus 1190 may be one or more of a free-space RF communication path1096, a waveguide RF communication path 1098, and/or a dielectric RFcommunication path 1100. For example, the RF bus 1190 may include atleast one data RF bus, at least one instruction RF bus, and at least onecontrol RF bus for intra-IC RF communications 1192 and the inter-IC RFcommunications 1194. In this example, intra-IC RF data communications1192 may occur over a free-space RF communication path 1096, while theintra-IC RF instruction and/or control communications 1192 may occurover a waveguide RF communication path 1098 and/or a dielectric RFcommunication path 1100 within the IC 1160 or 1162. Further, inter-IC RFdata communications 1194 may occur over a free-space RF communicationpath, while the intra-IC RF instruction and/or control communications1194 may occur over a waveguide RF communication path magneticcommunication path and/or a dielectric RF communication path within asupporting substrate of the ICs 1160-1162. As an alternative example,the inter- and intra-IC communications 1192-1194 may occur over multiplewaveguide RF communication paths, multiple dielectric RF communicationpaths, and/or multiple free-space RF communication paths (e.g., usedifferent carrier frequencies, distributed frequency patterns, TDMA,FDMA, CDMA, etc.).

FIG. 33 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that interfaces a plurality of integratedcircuits (ICs) 1160, 1162, and includes the RF bus controller 1088, aplurality of inter-IC RF buses 196, and an intra-IC RF bus 198. Each ofthe ICs 1160, 1162 includes a plurality of circuit modules 1170-1176 anda serial interface module 200-202. Each of the circuit modules 1170-1176includes a radio frequency (RF) bus transceiver 1180-1186.

In this embodiment, the RF bus controller 1088 is coupled to the ICs1160-1162 via a magnetic serial link 204 to control access to theinter-IC RF buses 1196 and to the intra-IC RF bus 1198. For instance,when a circuit module 1170-1176 has data to transmit to another circuitmodule 1170-1176 of the same IC or of a different IC, the requestingcircuit module 1170-1176 provides an RF bus request to the RF buscontroller 1088 via the wireline serial link 204 and the correspondingserial interface module 200-202. The serial link 204 and thecorresponding serial interface modules 200-202 may be a standardizedprotocol, a de-facto standard protocol, or a proprietary protocol. Forexample, the serial link 204 may be implemented via two or moreinductive interfaces such as inductive interfaces 22, 26.

The RF bus controller 1088 processes the RF bus request, as will bedescribed in greater detail with reference to figures that follow, todetermine at least one of whether the requestor needs access to one ofthe plurality of inter-IC RF buses 1196 or to the intra-IC RF bus 1198,how much data it has to send, the type of the data, the location of thetarget circuit module(s), the priority of the requestor, the priority ofthe data, etc. When the RF bus controller 1088 has determined how andwhen the requestor is to access the RF bus 1196 and/or 1198, the RF buscontroller 1088 provides an RF bus grant to the requestor via themagnetic link 204.

As shown, the intra-IC RF bus 1198 supports intra-IC RF communications1194 and the plurality of inter-IC RF buses 196 support correspondinginter-IC RF communications 1192. In this manner, multiple inter-IC RFcommunications 192 may be simultaneously occurring and may also occursimultaneously with one or more intra-IC RF communications 1194.

FIG. 34 is a schematic block diagram of another embodiment of RFinterface 1080 that interfaces a plurality of integrated circuits (ICs)1160, 1162, and includes the RF bus controller 1088, a plurality ofinter-IC RF buses 1196, and an intra-IC RF bus 1198. Each of the ICs1160, 1162 includes a plurality of circuit modules 1170-1176 and an RFtransceiver 210-212. Each of the circuit modules 1170-1176 includes aradio frequency (RF) bus transceiver 1180-1186 and the RF bus controller1088 includes the RF bus transceiver 1130.

In this embodiment, the RF bus controller 1088 is coupled to the ICs1160-1162 via a wireless link 214 to control access to the inter-IC RFbuses 1196 and to the intra-IC RF bus 1198. For instance, when a circuitmodule 1170-1176 has data to transmit to another circuit module1170-1176 of the same IC or of a different IC, the requesting circuitmodule 1170-1176 provides an RF bus request to the RF bus controller1088 via the wireless link 214 and the RF transceiver 210-212. Thewireless link 214 and the corresponding RF transceivers 210-212 may be astandardized protocol, a de-facto standard protocol, or a proprietaryprotocol.

The RF bus controller 1088 processes the RF bus request, as will bedescribed in greater detail with reference to Figures that follow, todetermine at least one of whether the requestor needs access to one ofthe plurality of inter-IC RF buses 1196 or to the intra-IC RF bus 1198,how much data it has to send, the type of the data, the location of thetarget circuit module(s), the priority of the requestor, the priority ofthe data, etc. When the RF bus controller 1088 has determined how andwhen the requestor is to access the RF bus 1196 and/or 1198, the RF buscontroller 1088 provides an RF bus grant to the requestor via thewireless link 214.

In one embodiment, the RF bus transceiver 1130 operates within a firstfrequency band and the intra-IC RF communications 192 and the inter-ICRF communications 1194 occur within the first frequency band. In thisinstance, the RF bus controller 1088 allocates at least onecommunication slot to the wireless interface link 214, allocates atleast one other communication slot for the intra-IC RF communications1192, and allocates at least another communication slot for the inter-ICRF communications 1194. The communication slots may be time divisionmultiple access (TDMA) slots, frequency division multiple access (FDMA)slot, and/or code division multiple access (CDMA) slots.

In another embodiment, the RF bus transceiver 1130 operates within afirst frequency band, the intra-IC RF communications 1192 occur withinthe first frequency band, and the inter-IC RF communications 1194 occurwithin a second frequency band. In this instance, the RF bus controller1088 allocates at least one communication slot in the first frequencyband to the wireless link 214 and allocates at least one othercommunication slot in the first frequency band for the intra-IC RFcommunications 192. The communication slots may be time divisionmultiple access (TDMA) slots, frequency division multiple access (FDMA)slot, and/or code division multiple access (CDMA) slots.

In another embodiment, the RF bus transceiver 1130 operates within afirst frequency band, the inter-IC RF communications 1194 occur withinthe second frequency band, and the intra-IC RF communications 1192 occurwithin the frequency band. In this instance, the RF bus controller 1088allocates at least one communication slot in the second frequency bandto the wireless link 214 and allocates at least one other communicationslot in the second frequency band for the inter-IC RF communications194. The communication slots may be time division multiple access (TDMA)slots, frequency division multiple access (FDMA) slot, and/or codedivision multiple access (CDMA) slots.

In another embodiment, the RF bus transceiver 1130 operates within afirst frequency band, the intra-IC RF communications 1192 occur withinthe second frequency band, and the inter-IC RF communications 1194 occurwithin a third frequency band. With the different types of communication(e.g., RF bus access, inter-IC, and intra-IC) occurring within differentfrequency bands, the different types of communication may occursimultaneously with minimal interference from each other.

FIG. 35 is a schematic block diagram of another embodiment of themillimeter wave interface 1080 that includes the RF bus controller 1088,a processing core 220, a memory system 222, a peripheral interfacemodule 224, a plurality of peripheral circuits 228-230, an RF memory bus242, and an RF I/O bus 244. Each of the processing core 220, the memorysystem 222, the peripheral interface module 224, and the plurality ofperipheral circuits 228-230 includes one or more RF bus transceivers232-240. The plurality of peripheral circuits 228-230 includes two ormore of a hard disk drive, a compact disk (CD) drive, a digital videodisk (DVD) drive, a video card, an audio card, a wireline network card,a wireless network card, a universal subscriber identity module (USIM)interface and/or security identification module (SIM) card, a USBinterface, a display interface, a secure digital input/output (SDIO)interface and/or secure digital (SD) card or multi-media card (MMC), acoprocessor interface and/or coprocessor, a wireless local area network(WLAN) interface and/or WLAN transceiver, a Bluetooth interface and/orBluetooth transceiver, a frequency modulation (FM) interface and/or FMtuner, a keyboard interface and/or keyboard, a speaker interface and/ora speaker, a microphone interface and/or a microphone, a globalpositioning system (GPS) interface and/or a GPS receiver, a camerainterface and/or an image sensor, a camcorder interface and/or a videosensor, a television (TV) interface and/or a TV tuner, a UniversalAsynchronous Receiver-Transmitter (UART) interface, a Serial PeripheralInterface (SPI) interface, a pulse code modulation (PCM) interface, etc.

In this embodiment, the peripheral interface module 224 includes a firstRF bus transceiver 236 and a second RF bus transceiver 238. The first RFbus transceiver 236 communicates via the RF memory bus 242 and thesecond RF bus transceiver communicates via the RF I/O bus 244. In thisinstance, the peripheral interface module 224 functions as an interfacefor one of the plurality of peripheral circuits 228-230 to communicatewith the processing core 220 and/or the memory system 222 via the RFmemory bus 242.

The RF bus controller 1088, which may be coupled to the processing core220, the memory system 222 and the peripheral interface module 224 via awireline serial link and/or a wireless link, controls access to the RFinput/output bus 244 among the plurality of peripheral circuits 228-230and the peripheral interface module 224 and controls access to the RFmemory bus 242 among the processing core 220, the memory system 222, andthe peripheral interface module 224. Note that the RF input/output bus244 supports at least one of: RF peripheral data communications, RFperipheral instruction communications, and RF peripheral control signalcommunications, where the RF peripheral control signal communicationsincludes an RF interrupt request communication, and/or an RF interruptacknowledgement communication.

The RF memory bus 242 supports at least one of: RF memory datacommunications, RF memory instruction communications, and RF memorycontrol signal communications. The RF memory bus may further support RFoperating system level communications and RF application levelcommunications.

FIG. 36 is a schematic block diagram of an embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088 and an RF bus 262. The processing module 250 includes a processingmodule RF bus transceiver 258 and the memory includes a memory RF bustransceiver 260. The processing module 250 and the baseband processingmodule 254 may be the same processing module or different processingmodules, where a processing module may be a single processing device ora plurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element (e.g., memory 252), which may be a singlememory device, a plurality of memory devices, and/or embedded circuitryof the processing module. Such a memory device may be a read-onlymemory, random access memory, volatile memory, non-volatile memory,static memory, dynamic memory, flash memory, cache memory, and/or anydevice that stores digital information. Note that when the processingmodule implements one or more of its functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, the memoryand/or memory element storing the corresponding operational instructionsmay be embedded within, or external to, the circuitry comprising thestate machine, analog circuitry, digital circuitry, and/or logiccircuitry. Further note that, the memory element stores, and theprocessing module executes, hard coded and/or operational instructionscorresponding to at least some of the steps and/or functions illustratedin FIGS. 33-41.

The baseband processing module 254 is coupled to convert outbound data264 into an outbound symbol stream 266. This may be done in accordancewith one or more wireless communication protocols including, but notlimited to, IEEE 802.11, Bluetooth, GSM, RFID, CDMA, Enhanced Data ratesfor GSM Evolution (EDGE), General Packet Radio Service (GPRS), newand/or current versions thereof, modifications thereof, extensionsthereof, combinations thereof, new WLAN standards, new cellular voiceand/or data standards, new wireless personal area networks (WPAN) orother protocol whether standard or not.

The RF section 256 converts the outbound symbol stream 266 into anoutbound RF signal 268. In an embodiment, the RF section 256 includes adigital to analog conversion module, an up-conversion module, and apower amplifier module. The digital to analog conversion module convertsthe outbound symbol stream 266 into an analog symbol stream. Theup-conversion module, which may be a direct conversion module or asuperheterodyne module, mixes the analog symbol stream with a localoscillation to produce an up-converted signal. The power amplifiermodule amplifies the up-converted signal to produce the outbound RFsignal 268. In another embodiment, the up-conversion module modulatesphase of the local oscillation based on phase information of the analogsymbol stream to produce the up-converted signal. The power amplifiermodule amplifies the up-converted signal based on a constant amplifierfactor or based on amplitude modulation information of the analog symbolstream to produce the outbound RF signal 268.

The RF section 256 is also coupled to and to convert an inbound RFsignal 270 into an inbound symbol stream 272. In one embodiment, the RFsection 256 includes a low noise amplifier module, a down-conversionmodule, and an analog to digital conversion module. The low noiseamplifier module amplifies the inbound RF signal 270 to produce anamplified inbound RF signal. The down conversion module, which may adirection conversion module or a superheterodyne module, mixes theamplified inbound RF signal with a local oscillation to produce ananalog inbound symbol stream. The analog to digital conversion moduleconverts the analog inbound symbol stream into the inbound symbol stream272.

The baseband processing module 254 is also coupled to convert theinbound symbol stream 272 into inbound data 274. This may be done inaccordance with one or more wireless communication protocols including,but not limited to, IEEE 802.11, Bluetooth, GSM, RFID, CDMA, EnhancedData rates for GSM Evolution (EDGE), General Packet Radio Service(GPRS), new and/or current versions thereof, modifications thereof,extensions thereof, combinations thereof, new WLAN standards, newcellular voice and/or data standards, and/or new wireless personal areanetworks (WPAN). Note that the inbound and outbound data 264, 274 may bevoice signals, audio signals, video signals, text signals, graphicssignals, short messaging signals, cellular data signals, etc.

The RF bus controller 1088 is coupled to control access to the RF bus262, which may include one or more waveguide RF communication paths, oneor more dielectric RF communication paths, one or more magneticcommunication paths and/or one or more free-space RF communicationpaths. In one embodiment, the processing module 250 generates theoutbound data 264, which is converted into an RF bus outbound datasignal 278 by the RF bus transceiver 258. The RF bus controller 1088controls conveyance of the RF bus outbound data signal 278 on the RF bus262. In another embodiment, the memory 252 provides the outbound data264, which is converted into the RF bus outbound data signal 278 by theRF bus transceiver 260.

The RF bus controller 1088 further functions to control access to the RFbus 262 for providing the inbound data 274 as an RF bus inbound datasignal 276 to the processing module RF bus transceiver 258 or to thememory RF bus transceiver 260. Note that in an embodiment of the RFtransceiver device, the baseband processing module 254 is coupled to theRF section 256 via a wireless digital-RF interface.

FIG. 37 is a schematic block diagram of an embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088 and an RF bus 262. The processing module 250 includes a processingmodule RF bus transceiver 258 and the memory includes a memory RF bustransceiver 260. In this embodiment, the baseband processing module 254includes an RF bus transceiver 280, which converts the inbound data 274into the RF bus inbound data signal 276 and converts the RF bus outbounddata signal 278 into the outbound data 264.

FIG. 38 is a schematic block diagram of an embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088 and an RF bus 262. The processing module 250 includes a processingmodule RF bus transceiver 258 and the memory includes a memory RF bustransceiver 260. In this embodiment, the RF section 256 receives the RFbus outbound data signal 278 and converts it into a baseband (BB) ornear baseband outbound data signal 290, which has a carrier frequency of0 Hz to a few MHz. Note that the RF section 256 may be coupled tomultiple antennas and/or coils (as shown) or may be coupled to a singleantenna/coil.

The baseband processing module 254 converts the baseband or nearbaseband outbound data signal 290 into the outbound data 264 inaccordance with a standardized wireless communication protocol (e.g.,GSM, EDGE, GPRS, CDMA, IEEE 802.11 Bluetooth), a modified standardwireless communication protocol (e.g., a modified version of GSM, EDGE,GPRS, CDMA, IEEE 802.11 Bluetooth), or a proprietary wirelesscommunication protocol (e.g., non-return to zero encode/decode, bi-phaseencode/decode). The baseband processing module 254 then converts theoutbound data 264 into the outbound symbol stream 266, which isconverted into the outbound RF signal 268 by the RF section 256.

The RF section 256 receives the inbound RF signal 270 and converts itinto the inbound symbol stream 272. The baseband processing module 254converts the inbound symbol stream 272 into the inbound data 274 andthen converts the inbound data 274 into a baseband or near basebandinbound data signal 292. The RF section 256 converts the baseband ornear baseband inbound data signal 292 into the RF bus inbound datasignal 276. Note that in an embodiment the baseband processing moduleconverts the outbound data 264 into the outbound symbol stream 266 andconverts the inbound symbol stream 272 into the inbound data 274 inaccordance with one or more of a wireless personal area network (WPAN)protocol (e.g., Bluetooth), a wireless local area network (WLAN)protocol (e.g., IEEE 802.11), a cellular telephone voice protocol (e.g.,GSM, CDMA), a cellular telephone data protocol (e.g., EDGE, GPRS), anaudio broadcast protocol (e.g., AM/FM radio), and a video broadcastprotocol (e.g., television).

In the various embodiments of an RF transceiver device as discussed withreference to FIGS. 36-38, the inbound and outbound RF signals 268 and270 may be in the same frequency band or a different frequency band thanthe RF bus inbound and outbound data signals 276 and 278. For example,the inbound and outbound RF signals 268 and 270 may have a carrierfrequency in a 2.4 GHz or 5 GHz frequency band while the RF bus inboundand outbound data signals 276 and 278 may have a carrier frequency in a60 GHz frequency band. As another example, the inbound and outbound RFsignals 268 and 270 and the RF bus inbound and outbound data signals 276and 278 may have a carrier frequency in a 60 GHz frequency band. Whenthe signals 268, 270, 276, and 278 are in the same frequency band, thefrequency band may be shared to minimize interference between thedifferent signals.

FIG. 39 is a diagram of an example of a frame of an RF transceiverdevice wireless communication that shares a frequency band and minimizesinterference between the different signals 268, 270, 276, and 278. Inthis example, the frame includes an inbound RF signal slot 300, an RFbus inbound data signal slot 302, an RF bus outbound data signal 304,and an outbound RF signal 306. The slots 300-306 may be TDMA slots, CDMAslots, or FDMA slots, which may be reallocated on a frame by frame basisby the RF bus controller 1088. For example, the processing module 250and/or the baseband processing module 254 may request one or more slotsfrom the RF bus controller 1088 for the inbound RF signal 270, theoutbound RF signal 268, the RF bus inbound data signal 276, and/or theRF bus outbound data signal 278. Note that the frame may include anadditional slot for bus access communications if the RF bus requests andRF bus grants are communicated wirelessly within the same frequency bandas the signals 268, 270, 276, and 278.

FIG. 37 is a logic diagram of an embodiment of a method of resourceallocation for an intra-device wireless communication that begins atstep 1310 where the processing module 250 and/or the baseband processingmodule 254 determine a potential overlapping of one of the RF businbound data signal 276 and the RF bus outbound data signal 278 with oneof the inbound

RF signal 270 and the outbound RF signal 268. In this embodiment, thesignals 268, 270, 276, and 278 may be transmitted and/or received at anytime without a structured ordering of the signals (in other words, thesignals do not have allocated slots). If a potential overlap is notdetected (i.e., the transmission or reception of one signal will notinterfere with the transmission or reception of another signal), theprocess proceeds to step 1312 where the RF bus communication (e.g., theRF bus inbound or outbound data signal 276 or 278) or the inbound oroutbound RF signal 270 or 268 is transmitted or received.

If a potential overlap is detected, the process proceeds to step 1314where the frequency and/or phase of the RF bus inbound data signal 276and/or of the RF bus outbound data signal 278 is adjusted. For example,if a potential overlap is detected, the phase of the RF buscommunications (e.g., signals 276 or 278) may be adjusted to beorthogonal with the inbound or outbound RF signals 270 or 268 therebysubstantially reducing the received signal strength of the orthogonalsignal. As another example, the carrier frequency may be adjusted by afrequency offset such that it has a different carrier frequency than theinbound or outbound RF signal 270 or 268.

The process then proceeds to step 1316 where blocking of the inbound RFsignal 270 or the outbound RF signal 268 for the RF bus communication isenabled. As such, by adjusting the phase and/or frequency of the RF buscommunication, the inbound or outbound RF signal 270 or 268 may betreated as an interferer with respect to the RF bus communications thatcan be substantially blocked. Thus, if a potential overlap exists, theRF bus communications are adjusted such that they experience acceptablelevels of interference from the inbound or outbound RF signals.

FIG. 41 is a diagram of another example of a frame of an RF transceiverdevice wireless communication that shares a frequency band and minimizesinterference between the different signals 268, 270, 276, and 278. Inthis example, the frame includes the inbound RF signal slot 1300; anoutbound RF signal, an RF bus inbound data signal, or composite signalslot 1320, and the RF bus outbound data signal 1304. The slots 1300,1320, and 1304 may be TDMA slots, CDMA slots, or FDMA slots, which maybe reallocated on a frame by frame basis by the RF bus controller 1088.Note that the frame may include an additional slot for bus accesscommunications if the RF bus requests and RF bus grants are communicatedwirelessly within the same frequency band as the signals 268, 270, 276,and 278.

In this example, the baseband processing module 254 processes the datafor the outbound RF signal 268 and the RF bus inbound data signal 276.As such, the baseband processing module 254 has knowledge of whichsignal it is processing and thus can request allocation of a resourcefor the appropriate signal (e.g., 268 or 276). In addition, the basebandprocessing module 254 may simultaneously process the data for theoutbound RF signal 268 and the RF bus inbound data signal 276 via acomposite signal.

FIG. 42 is a diagram of an example of mapping data of an RF transceiverdevice wireless communication into a composite signal. In this example,the baseband processing module 254 combines bits 322 of the outbounddata 264 and bits 1324 of the inbound data 274 to produce compositedata. In this example, the bits 1322 of the outbound data 264 are leastsignificant bits of the composite data and the bits 324 of the inbounddata 274 are most significant bits of the composite data. The basebandprocessing module then encodes the composite data to produce encodeddata; interleaves the encoded data to produce interleaved data; maps theinterleaved data to produce mapped data; and converts the mapped datafrom the frequency domain to the time domain to produce a baseband ornear baseband composite outbound data signal. The RF section 256converts the baseband or near baseband composite outbound data signalinto a composite outbound RF signal, wherein the composite outbound RFsignal includes the outbound RF signal 268 and the RF bus inbound datasignal 276.

The RF bus transceiver 258 or 260 receives the composite outbound RFsignal, converts it into the baseband or near baseband compositeoutbound data signal. A baseband processing module within the RF bustransceiver 258 or 260 converts the baseband or near baseband compositeoutbound data signal from the time domain to the frequency domain toproduce the mapped data; demaps the mapped data to produce interleaveddata; deinterleaves the interleaved data to produce encoded data; anddecodes the encoded data to produce the inbound data 274 and outbounddata 264. The RF bus transceiver 258 or 260 is programmed to ignore theoutbound data 264 bits of the composite data such that the resultingrecovered data from the composite outbound RF signal is the inbound data274.

An RF transceiver within the target of the outbound RF signal 268 treatsthe composite outbound RF signal as a lower mapped rate outbound RFsignal. As shown, the composite data is mapped using a 16 QAM(quadrature amplitude mapping scheme). A first quadrant has mapped bitsof 0000, 0001, 0010, and 0011; a second quadrant has mapped bits of0100, 0101, 0110, and 0111; a third quadrant has mapped bits of 1100,1101, 1110, and 1111; and a fourth quadrant has mapped bits of 1000,1001, 1010, and 1011. If the RF transceiver within the target uses aQPSK (quadrature phase shift keying), if the composite signal is withinthe first quadrant, the RF transceiver will interpret this as a mappedvalue of 00, if the composite signal is within the second quadrant, theRF transceiver will interpret this as a mapped value of 01, if thecomposite signal is within the third quadrant, the RF transceiver willinterpret this as a mapped value of 11, and if the composite signal iswithin the fourth quadrant, the RF transceiver will interpret this as amapped value of 10.

In general, since the RF bus transceivers should experiencesignificantly greater signal integrity than the RF transceiver withinthe target, the RF bus transceivers can operate at a higher mapping ratethan the RF transcevier within the target. As such, the basebandprocessing module may convert the bits 1322 of the outbound data 264 andthe bits 1324 of the inbound data 274 into the baseband or near basebandcomposite outbound data signal using one of N-QAM (quadrature amplitudemodulation) and N-PSK (phase shift keying), wherein N equals 2^(x) and xequals the number of bits of the outbound data 264 plus the number ofbits of the inbound data 274.

FIG. 43 is a schematic block diagram of another embodiment of an RFtransceiver device that includes a processing module 250, memory 252, abaseband processing module 254, an RF section 256, the RF bus controller1088, an RF bus 262, a peripheral interface module 224, an RF I/O bus244, and a plurality of peripheral circuits 228-230. Each of theprocessing module 250, the memory 242, the peripheral interface module224, and the peripheral circuits 228-230 includes at least one RF bustransceiver 235, 236, 238, 240, 258, and 260.

In this embodiment, a dual bus structure is shown where the RF buscontroller 1088 controls access to the RF bus 262 for providing the RFbus outbound data signal 278 from one of the processing module RF bustransceiver 258, the memory RF bus transceiver 260, and the peripheralinterface RF bus transceiver 236. The RF bus controller 1088 alsocontrols access to the RF bus 262 for providing the RF bus inbound datasignal 276 to one of the processing module RF bus transceiver 258, thememory RF bus transceiver 260, and the peripheral interface RF bustransceiver 236.

The RF bus controller 1088 further controls access to a peripheral I/ORF bus 244 among a plurality of peripheral circuits 228-230. In anembodiment, when access is granted to one of the plurality of peripheralcircuits 228-230, it provides an inbound RF peripheral data signal tothe peripheral interface RF bus transceiver 238 or receives an outboundRF peripheral data signal from the peripheral interface RF bustransceiver 238. The inbound or outbound RF peripheral data signal maydata from the processing module 250, may be data from the memory 252,may be the RF bus inbound data signal 276, may be the RF bus outbounddata signal 278, may the inbound data 274, and/or may be the outbounddata 264. It should be noted that the RF bus 262 and RF I/O bus 244 canbe implemented with different technologies as well as differentfrequencies. In one example, the RF bus 262 can operate using inductivecoupling and one or more magnetic communication path and RF I/O bus 244can operate using one or more millimeter wave communication paths. Otherexamples are likewise possible.

FIG. 44 is a schematic block diagram of another embodiment of an RFtransceiver device that includes a processing module 1330, memory 1332,a baseband processing module 254, an RF section 256, the RF buscontroller 1088, a bus structure 1334, a peripheral interface module224, an external RF bus 1336, and a plurality of peripheral circuits228-230. Each of the peripheral interface module 224 and the peripheralcircuits 228-230 includes at least one RF bus transceiver 235, 238, and240. The processing module 1330 and the baseband processing module 254may be the same processing module or different processing modules, wherea processing module may be a single processing device or a plurality ofprocessing devices. Such a processing device may be a microprocessor,micro-controller, digital signal processor, microcomputer, centralprocessing unit, field programmable gate array, programmable logicdevice, state machine, logic circuitry, analog circuitry, digitalcircuitry, and/or any device that manipulates signals (analog and/ordigital) based on hard coding of the circuitry and/or operationalinstructions. The processing module may have an associated memory and/ormemory element (e.g., memory 332), which may be a single memory device,a plurality of memory devices, and/or embedded circuitry of theprocessing module. Such a memory device may be a read-only memory,random access memory, volatile memory, non-volatile memory, staticmemory, dynamic memory, flash memory, cache memory, and/or any devicethat stores digital information. Note that when the processing moduleimplements one or more of its functions via a state machine, analogcircuitry, digital circuitry, and/or logic circuitry, the memory and/ormemory element storing the corresponding operational instructions may beembedded within, or external to, the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.

In this embodiment, the processing module 1330, the memory 1332, thebaseband processing module 254, and the peripheral interface module 224are coupled together via a bus structure 1334, which may be an advancedhigh-performance (AHB) bus matrix. As such, data between these modulesoccurs with the bus. The peripheral interface module 224 is coupled tothe plurality of peripheral circuits 228-230 via the external RF bus1336, which may be one or more waveguide RF communication paths, one ormore dielectric RF communication paths, one or more magneticcommunication paths and/or one or more free-space RF communicationpaths.

In this instance, the RF bus controller 1088 controls access theexternal RF bus 336 among a plurality of peripheral circuits 228-230. Inan embodiment, when access is granted to one of the plurality ofperipheral circuits 228-230, it provides an inbound RF peripheral datasignal to the peripheral interface RF bus transceiver 238 or receives anoutbound RF peripheral data signal from the peripheral interface RF bustransceiver 238. The inbound or outbound RF peripheral data signal maydata from the processing module 1330, may be data from the memory 1332,may the inbound data 274, and/or may be the outbound data 264.

FIG. 45 is a schematic block diagram of another embodiment of an RFIDsystem that includes at least one RFID transceiver, at least one RFIDtag, and a network connection module 1352. The RFID reader 1054 includesa reader processing module 340, an RFID transceiver 1342, and an RF bustransceiver 1344. The RFID tag 1060 includes a power recovery module1346, a tag processing module 1348, and a transmit section 1350. Thenetwork connection module 1352 includes an RF bus transceiver 1354.

The reader processing module 1340 may be a single processing device or aplurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element, which may be a single memory device, aplurality of memory devices, and/or embedded circuitry of the processingmodule. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, cache memory, and/or any device that storesdigital information. Note that when the processing module implements oneor more of its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory and/or memory elementstoring the corresponding operational instructions may be embeddedwithin, or external to, the circuitry comprising the state machine,analog circuitry, digital circuitry, and/or logic circuitry.

In an embodiment, reader processing module 1340 encodes outbound RFIDdata 1356 to produce outbound RFID encoded data 1358. The encoding maybe done in accordance with an RFID protocol such as FM0, FM1, etc., maybe a modified RFID protocol, and/or a proprietary protocol. Note thatthe reader processing module 1340 may generate the outbound RFID data1356 or receive it from the network connection module 1352 via the RFbus 1374. Further note that the outbound RFID data 1356 may be a requestfor status information from one or more RFID tags, may be data forstorage and/or processing by one or more RFID tags, may be commands tobe performed by one or more RFID tags, etc.

The RFID transceiver 1342 is coupled to convert the outbound RFIDencoded data 358 into an outbound RF RFID signal 1360. One or more ofthe RFID tags 1060 receives the outbound RF RFID signal 1360 via anantenna coupled to the power recovery module 1346. The power recoverymodule 1346 is coupled to produce a supply voltage (Vdd) 1362 from theoutbound RF RFID signal 1360 and to produce a received RF RFID signal1364.

The tag processing module 1348 may be a single processing device or aplurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module may have an associatedmemory and/or memory element, which may be a single memory device, aplurality of memory devices, and/or embedded circuitry of the processingmodule. Such a memory device may be a read-only memory, random accessmemory, volatile memory, non-volatile memory, static memory, dynamicmemory, flash memory, cache memory, and/or any device that storesdigital information. Note that when the processing module implements oneor more of its functions via a state machine, analog circuitry, digitalcircuitry, and/or logic circuitry, the memory and/or memory elementstoring the corresponding operational instructions may be embeddedwithin, or external to, the circuitry comprising the state machine,analog circuitry, digital circuitry, and/or logic circuitry.

The tag processing module 1348 is coupled to recover the outbound RFIDdata 1356 from the received RF RFID signal 1364 and to generate tag RFIDdata 1366 in response thereto. The tag RFID data 1366 may be response toan inquiry, may be an acknowledgement of data storage, may be anacknowledgement of a program update, and/or may be an acknowledgement ofcompletion of execution of a command. The transmit section 1350 iscoupled to convert the tag RFID data 1366 into and inbound RF RFIDsignal 1368 using a back-scatter technique or some other RF modulationprotocol.

The RFID transceiver 1342 is further coupled to convert the inbound RFRFID signal 1368 into inbound RFID encoded data 1370. In one embodiment,the RFID transceiver 1342 includes a transmitter section and a receiversection.

The reader processing module 1340 decodes the inbound RFID encoded data1370 to produce inbound RFID data 1372. The decoding may be done inaccordance with an RFID protocol such as FM0, FM1, etc., may be amodified RFID protocol, and/or a proprietary protocol.

In an embodiment, the reader RF bus transceiver 1344 exchanges at leastone of the inbound RFID data 1372 and the outbound RFID data 1356 withthe network RF bus transceiver 1354 via the RF bus 1374. Note that theRF bus 1374 may be one or more waveguide RF communication paths, one ormore dielectric RF communication paths, one or more magneticcommunication paths and/or one or more free-space RF communicationpaths.

In one embodiment of the RFID system, the inbound and outbound RF RFIDsignals 1360 and 1368 have a carrier frequency in a first frequency bandand the RF bus 374 supports RF bus communications having a carrierfrequency in a second frequency band. For example, the first or thesecond frequency band may be a 60 GHz frequency band. In this instance,the RFID communications and the RF bus communications provide littleinterference for one another.

FIG. 46 is a schematic block diagram of another embodiment of an RFIDsystem that includes a network connection module 1352, an RF bus 1372,and an RF bus controller 1088. Each of the RFID readers 1454-1458includes the RFID transceiver 342 and the RF bus transceiver 1344. Thenetwork connection module 1352 includes the RF bus transceiver 1354 anda WLAN (wireless local area network) or WPAN (wireless personal areanetwork) transceiver 1380.

In an embodiment, the RF bus controller 1088 controls access to carrierfrequencies within a frequency band, wherein the inbound and outbound RFRFID signals 1360 and 1368 having a carrier frequency within thefrequency band and the RF bus 1374 supports RF bus communications havinga carrier frequency within the frequency band.

In another embodiment, the inbound and outbound RF RFID signals 1360 and1368 have a carrier frequency in a first frequency band. The RF bus 1374supports RF bus communications having a carrier frequency in a secondfrequency band. The WLAN transceiver 1380 transceives RF signals havinga carrier frequency in a third frequency band, wherein the first, secondor the third frequency bands is within a 60 GHz or other millimeter wavefrequency band.

In another embodiment, the inbound and outbound RF RFID signals 1360 and1368 have a carrier frequency within a frequency band and the RF bus1374 supports RF bus communications having the carrier frequency withinthe same frequency band. The WLAN transceiver 1380 transceives RFsignals having a carrier frequency outside of the frequency band. Inthis instance, the RF bus controller 1088 controls access to carrierfrequencies within the frequency band using a TDMA allocation, an FDMAallocation, a CDMA allocation, a CSMA with collision avoidance scheme, apolling-response scheme, a token passing scheme, and/or a combinationthereof.

In another embodiment, the inbound and outbound RF RFID signals 1360 and1368 have a carrier frequency within a frequency band, the RF bus 1374supports RF bus communications having a carrier frequency within thefrequency band, and the WLAN transceiver 1380 transceives RF signalshaving a carrier frequency within the frequency band. In this instance,the RF bus controller 1088 controls access to carrier frequencies withinthe frequency band using a TDMA allocation, an FDMA allocation, a CDMAallocation, a CSMA with collision avoidance scheme, a polling-responsescheme, a token passing scheme, and/or a combination thereof.

FIG. 47 is a schematic block diagram of an embodiment of an RFID reader1054 that includes a processing module 390, a transmitter section 392,and a receiver section 394. The processing module 390 may be a singleprocessing device or a plurality of processing devices. Such aprocessing device may be a microprocessor, micro-controller, digitalsignal processor, microcomputer, central processing unit, fieldprogrammable gate array, programmable logic device, state machine, logiccircuitry, analog circuitry, digital circuitry, and/or any device thatmanipulates signals (analog and/or digital) based on hard coding of thecircuitry and/or operational instructions. The processing module mayhave an associated memory and/or memory element, which may be a singlememory device, a plurality of memory devices, and/or embedded circuitryof the processing module. Such a memory device may be a read-onlymemory, random access memory, volatile memory, non-volatile memory,static memory, dynamic memory, flash memory, cache memory, and/or anydevice that stores digital information. Note that when the processingmodule implements one or more of its functions via a state machine,analog circuitry, digital circuitry, and/or logic circuitry, the memoryand/or memory element storing the corresponding operational instructionsmay be embedded within, or external to, the circuitry comprising thestate machine, analog circuitry, digital circuitry, and/or logiccircuitry.

In operation, the processing module 390 is coupled to encode tag inquirydata 408 to produce encoded tag inquiry data 410. The encoding may bedone in accordance with an RFID protocol such as FM0, FM1, etc., may bea modified RFID protocol, and/or a proprietary protocol. Note that theprocessing module 390 may generate the tag inquiry data 408 or receiveit from a network connection module 352 via the RF bus 374. Further notethat the tag inquiry data 408 may be a request for status informationfrom one or more RFID tags, may be data for storage and/or processing byone or more RFID tags, may be commands to be performed by one or moreRFID tags, etc.

For the processing module 390 to receive the tag inquiry data 408 fromthe network connection module 352, the network connection module 352generates the data 408 and the RF bus transceiver 354 converts it intoan inbound RF bus signal 402. The receiver section 394, which will bedescribed in greater detail with reference to FIG. 29, converts theinbound RF bus signal 402 into inbound RF bus encoded data 404. Theprocessing module 390 decodes the inbound RF bus encoded data 404 toproduce inbound RF bus data 406, which, in this example, is the taginquiry data 408. Note that other data may be received from the networkconnection module 352 in this manner.

The transmitter section 392 is coupled to convert the encoded taginquiry data 410 into an outbound RF tag inquiry signal 412. If the taginquiry data 408 instructs the RFID tag to respond, the receiver section394 receives the inbound RF tag response signal 414.

The receiver section 394 converts the inbound RF tag response signal 414into encoded tag response data 416. The processing module 390 decodesthe encoded tag response data 416 to recover the tag response data 418.If the tag response data 418 is to be provided to the network connectionmodule 352, the processing module 390 utilizes the tag response data 418as the outbound RF bus data 396 and encodes the outbound RF bus data 396to produce outbound RF bus encoded data 398.

The transmitter section 392 converts the outbound RF bus encoded data398 into an outbound RF bus signal 400. The network connection module352 receives the outbound RF bus signal 400 via the RF bus and its RFbus transceiver 354. Note that other data may be transmitted to thenetwork connection module 352 in this manner.

In an embodiment, the processing module 390 further functions toarbitrate between RF bus communications (e.g., inbound and outbound RFbus signals 400 and 402) and RFID tag communications (e.g., outbound RFtag inquiry signal 412 and inbound RF tag response signal 414). In thismanner, interference between the RF bus communications and the RFID tagcommunications is minimal. Note that in an embodiment, the RF buscommunications and the RFID tag communications having a carrierfrequency in a 60 GHz frequency band or a frequency band used forinductive coupling between one or more devices.

FIG. 48 is a schematic block diagram of another embodiment of a devicethat includes a plurality of integrated circuits (ICs) 500-502 and an RFbus structure 528. Each of the plurality of ICs 500-502 includes aplurality of circuit modules 504-506, 508-510, a switching module 512,514, an RF bus transceiver 516, 518, an antenna interface 520, 522, andan antenna structure 534, 526 such as a coil or other antenna. Thecircuit modules 504-510 may be any type of digital circuit, analogcircuit, logic circuit, and/or processing circuit. For example, one ofthe circuit modules 504-510 may be, but is not limited to, amicroprocessor, a component of a microprocessor, cache memory, read onlymemory, random access memory, programmable logic, digital signalprocessor, logic gate, amplifier, multiplier, adder, multiplexer, etc.

In this embodiment, the circuit modules 504-506 and 508-510 of an IC500, 502 share an RF bus transceiver 516, 518 for external ICcommunications (e.g., intra-device communications and/or inter-ICcommunications) and communicate via the switching module 512, 514 forinternal IC communications (e.g., intra-IC communications). Theswitching module 512, 514 may include a wireline bus structure (e.g.,AHB) and a plurality of switches, multiplexers, demultiplexers, gates,etc. to control access to the wireline bus structure and/or access tothe RF bus transceiver.

The antenna interface 520, 522 may include one or more of a transformerbalun, an impedance matching circuit, and a transmission line to providea desired impedance, frequency response, tuning, etc. for the antennastructure 524, 526. The antenna structure 524, 526 may be implemented asdescribed in co-pending patent application entitled AN INTEGRATEDCIRCUIT ANTENNA STRUCTURE, having a filing date of Dec. 29, 2006, and aSer. No. 11/648,826.

The RF bus structure 528, which may be one or more waveguide RFcommunication paths, one or more dielectric RF communication paths,magnetic communication paths and/or one or more free-space RFcommunication paths, receives outbound RF bus signal from the antennastructure 524, 526 and provides it to the antenna structure 524, 526 ofanother one of the plurality of ICs 500-502.

In an embodiment, the switching module 512, 514 performs the method ofFIG. 49 to control internal IC communications and external ICcommunications. The method begins at step 530 where the switching module512, 514 receives an outbound bus communication from one of theplurality of circuit modules 504-510. The process then proceeds to step532 where the switching module 512, 514 determines whether the outboundbus communication is an internal IC communication or an external ICcommunication.

When the outbound bus communication is an internal IC communication, theprocess proceeds to step 534 where the switching module 512, 514provides the outbound bus communication to another one of the pluralityof circuit modules 504-506, 508-510. In this instance, the switchingmodule 512, 514 utilizes the wireline bus structure and the appropriateswitches, multiplexers, etc. to couple one circuit module 504 to theother 506 for the conveyance of the outbound bus communication.

When the outbound bus communication is an external IC communication, theswitching module 512, 514 outputs the outbound bus communication to theRF bus transceiver 516, 518, which converts the outbound buscommunication into an outbound RF bus signal. The antenna interface andthe antenna structure provide the outbound RF bus signal to the RF busstructure 528 for conveyance to another circuit module of another IC.

For an inbound RF bus signal, the antenna structure 524, 526 receivesthe inbound RF bus signal from the RF bus structure 528 and provides itto the RF bus transceiver 516, 518 via the antenna interface 520, 522.The RF bus transceiver 516, 518 converts the inbound RF bus signal intoan inbound bus communication. The switching module 512, 514 interpretsthe inbound bus communication and provides it to the addressed circuitmodule or modules.

FIG. 50 is a schematic block diagram of an embodiment of an RF buscontroller 1088 that includes an interface 730 and a processing module732. The processing module 732 may be a single processing device or aplurality of processing devices. Such a processing device may be amicroprocessor, micro-controller, digital signal processor,microcomputer, central processing unit, field programmable gate array,programmable logic device, state machine, logic circuitry, analogcircuitry, digital circuitry, and/or any device that manipulates signals(analog and/or digital) based on hard coding of the circuitry and/oroperational instructions. The processing module 732 may have anassociated memory and/or memory element, which may be a single memorydevice, a plurality of memory devices, and/or embedded circuitry of theprocessing module. Such a memory device may be a read-only memory,random access memory, volatile memory, non-volatile memory, staticmemory, dynamic memory, flash memory, cache memory, and/or any devicethat stores digital information. Note that when the processing module732 implements one or more of its functions via a state machine, analogcircuitry, digital circuitry, and/or logic circuitry, the memory and/ormemory element storing the corresponding operational instructions may beembedded within, or external to, the circuitry comprising the statemachine, analog circuitry, digital circuitry, and/or logic circuitry.Further note that, the memory element stores, and the processing module732 executes, hard coded and/or operational instructions correspondingto at least some of the steps and/or functions illustrated in FIGS.51-61.

The interface 730 may be a wireline interface (e.g., an Ethernetconnection, a USB connection, an I2C connection, an I2S connection, orany other type of serial interface) or a wireless interface (e.g., WLAN,WPAN, Intra-device communication, etc.) If the interface 730 is awireless interface, it may include a transceiver module to access acontrol RF communication path having a different frequency than afrequency of the RF bus, a transceiver module to access a control timeslot of a time division multiple access partitioning of the RF bus, atransceiver module to access a control frequency slot of a frequencydivision multiple access partitioning of the RF bus, or a transceivermodule to access the RF bus for communicating the intra-device RF busaccess requests and allocations via a carrier sense multiple access(CSMA) protocol. Regardless of the type of interface, the interface 732is coupled for communicating intra-device RF bus access requests andallocations.

FIG. 51 is a logic diagram of method for controlling access to an RF busthat is performed by the RF bus controller 1088. The method begins atstep 734 where the RF Bus controller 1088 receives an access request toan RF bus via the interface 730. The access request may be received in avariety of ways. For example, the access request may be received inresponse to a polling request, in an allocated time division multipleaccess (TDMA) slot, in response to a token ring passing scheme, inaccordance with a carrier sense multiple access (CSMA) protocol of a RFbus control resource, in accordance with an interrupt protocol, in anallocated frequency division multiple access (FDMA) slot, and/or in anallocated code division multiple access (CDMA) slot.

The method continues at step 736 where the RF bus controller 1088determines RF bus resource availability. This step may also includedetermining an RF bus protocol based on the access request. The RF busprotocol may be a standardized wireless protocol (e.g., GSM, EDGE, GPRS,IEEE 802.11, Bluetooth, etc), a proprietary wireless protocol, and/or amodified standardized wireless protocol (based on one of the standardprotocols but modified, for instance, using an IEEE 802.11 protocol butskipping the interleaving).

The method branches at step 738 based on whether sufficient RF busresources are availability. When sufficient RF bus resources areavailable, the process proceeds to step 740 where the RF bus controllerallocates, via the interface, at least one RF bus resource in responseto the access request. Note that the RF bus resources include, but arenot limited to, a Single Input Single Output (SISO) channel, a MultipleInput Multiple Output (MIMO) channel, multiple SISO channels, multipleMIMO channels, null-reinforce multipath patterning (e.g., use multipathreinforced areas for RF bus communications between two ICs and multipathnulls to block RF bus communications between two ICs), frequency bandselection, a TDMA slot, a CDMA slot, an FDMA slot, an unused free-spaceRF communication path or channel, an unused waveguide RF communicationpath or channel, an unused dielectric RF communication path or channel,and/or any other medium or portioning scheme for transmitting RFsignals.

When sufficient RF bus resources are not available, the method proceedsto step 742 where the RF bus controller 1088 determining what RF busresources are available. The method then proceeds to step 744 where theRF bus controller determines whether the access request can beadequately accommodated by the available RF bus resources. In otherwords, optimal servicing of the original resource request would requirea certain level of RF bus resource allocation based on the amount ofdata to be transmitted, the type of data being transmitted, therequestor of the RF bus access, the target(s) of the data, etc. In thisinstance, the optimal amount of RF bus resources is not available, butthere are some resources available and the RF bus controller isdetermining whether this less than optimal amount of RF bus resourcescan adequately accommodate (e.g., less than optimal, but acceptable) therequest. For example, assume that for a particular RF bus accessrequest, the optimal amount of RF bus resources supports a data transferrate of 100 Mega-bits per second, but that the available RF busresources can only accommodate 66 Mega-bits per second. In this example,the RF bus controller 1088 will determine whether the 66 Mbps rate willaccommodate the request (i.e., won't suffer loss of data integrity, lossof data continuity, etc.).

When the access request can be accommodated by the available RF busresources, the method proceeds to step 746 where the RF bus controller1088 allocates the available RF bus resources to for the access request.If, however, the access request cannot be accommodated by the availableRF bus resources, the method proceeds to step 748 where the RF buscontroller queues the access request.

FIG. 52 is a diagram of another embodiment of a frame 750 of an RF buscommunication that includes a request control slot 752, an allocationcontrol slot 754, and a data slot(s) 756. In this embodiment, the slots752-756 may be TDMA slots, FDMA slots, or CDMA slots on a single channelor multiple channels. Access to the request control slot 752 beallocated to the requesting ICs or circuit modules by the RF buscontroller 1088 in a round robin manner, in a poll-request manner, in aCSMA with collision avoidance manner, etc.

In this embodiment, when an IC or circuit module has data to transmitvia an RF bus (e.g., intra-IC RF bus and/or inter-IC RF bus), therequesting IC or circuit module provides its request within the requestcontrol slot 752. The requesting IC or circuit module waits until itdetects an RF bus grant from the RF bus controller via the allocationcontrol slot 754. The RF bus grant will indicate the RF bus resourcesbeing allocated, the duration of the allocation, etc. and may furtherinclude an indication of the RF bus protocol to be used. Once therequesting IC or circuit module has been granted access, it transmitsits data via the allocated RF bus resources during the appropriate dataslots 756.

FIG. 53 is a logic diagram of method for determining RF bus resourceavailability of step 736 of FIG. 65. This method begins at step 760where the RF bus controller determines transmission requirements of theaccess request, RF bus capabilities of requestor, and/or RF buscapabilities of target. The transmission requirements include one ormore of amount of information to be conveyed, priority level ofrequestor (e.g., application level priority, operating system levelpriority, continuous data priority, discontinuous data priority, etc.),priority level of the information to be conveyed (e.g., applicationdata, interrupt data, operating system data, etc.), real-time ornon-real-time aspect of the information to be conveyed, and/orinformation conveyance integrity requirements.

The conveyance integrity requirements relate to the sensitivity of thedata, the requestor, and/or the target is to data transmission errorsand the ability to correct them. Thus, if any of the target or requestoris intolerant to data transmission errors and/or they cannot becorrected, the data needs to be transmitted with the highest level ofintegrity to insure that very few data transmission errors will occur.Conversely, if the requestor and target can tolerate data transmissionerrors and/or can correct them; lower levels of integrity can be used toprovide an adequate RF bus communication. Thus, the RF bus controllermay consider the RF communication paths available (e.g., waveguide,dielectric, free-space), the level of rate encoding, the level ofinterleaving, the level of error correction, and/or the level ofacknowledgement. For example, a request that can tolerate datatransmission errors, the data may be bi-phase encoded with nointerleaving and rate encoding and transmitted over a free-space RFcommunication path, where a request that cannot tolerate datatransmission errors, the data will be encoded using the rate encoding,it will be interleaved, error correction (e.g., forward error correct)enabled, and transmitted over a waveguide RF communication path.

The method then proceeds to step 762 where the RF bus controllerdetermines required RF bus resources based on the at least one of thetransmission requirements, the RF bus capabilities of the requestor, andthe RF bus capabilities of the target. The method then proceeds to step764 where the RF bus controller determines whether the required RF busresources are available for allocation.

FIG. 54 is a logic diagram of another method for controlling access toan RF bus that is performed by the RF bus controller 1088. The methodbegins at step 734 where the RF Bus controller 1088 receives an accessrequest to an RF bus via the interface 730. The access request may bereceived in a variety of ways. For example, the access request may bereceived in response to a polling request, in an allocated time divisionmultiple access (TDMA) slot, in response to a token ring passing scheme,in accordance with a carrier sense multiple access (CSMA) protocol of aRF bus control resource, in accordance with an interrupt protocol, in anallocated frequency division multiple access (FDMA) slot, and/or in anallocated code division multiple access (CDMA) slot.

The method continues at step 736 where the RF bus controller 1088determines RF bus resource availability. This step may also includedetermining an RF bus protocol based on the access request. The RF busprotocol may be a standardized wireless protocol (e.g., GSM, EDGE, GPRS,IEEE 802.11, Bluetooth, etc), a proprietary wireless protocol, and/or amodified standardized wireless protocol (based on one of the standardprotocols but modified, for instance, using an IEEE 802.11 protocol butskipping the interleaving).

The method branches at step 738 based on whether sufficient RF busresources are availability. When sufficient RF bus resources areavailable, the process proceeds to step 740 where the RF bus controllerallocates, via the interface, at least one RF bus resource in responseto the access request. Note that the RF bus resources include, but arenot limited to, a Single Input Single Output (SISO) channel, a MultipleInput Multiple Output (MIMO) channel, multiple SISO channels, multipleMIMO channels, null-reinforce multipath patterning (e.g., use multipathreinforced areas for RF bus communications between two ICs and multipathnulls to block RF bus communications between two ICs), frequency bandselection, a TDMA slot, a CDMA slot, an FDMA slot, an unused free-spaceRF communication path or channel, an unused waveguide RF communicationpath or channel, an unused dielectric RF communication path or channel,and/or any other medium or portioning scheme for transmitting RFsignals.

When sufficient RF bus resources are not available, the method proceedsto step 766 where the RF bus controller 1088 determines whether priorityof requestor is at or above a first priority level. The priority levelmay be user defined, system defined, an ordering based on data type(e.g., operating system level data, application level data, interruptdata, real-time or continuous data v. non-real-time or discontinuousdata, etc.), system level based (e.g., processing module, memory,peripheral device, etc. in order) and/or any other priority and/orordering scheme. When the request is not above the 1^(st) level, themethod proceeds to step 768 where the RF bus controller queues therequest.

When priority of the requestor is at or above the first priority level,the method proceeds to step 770 where the RF bus controller 1088determines whether allocated RF bus resources can be reallocated to makeavailable the sufficient RF bus resources. In this determination, the RFbus controller is determining whether existing RF bus communications canhave their RF bus resources reallocated such that their level of serviceis below optimal, but still acceptable, to make sufficient resourcesavailable for the 1^(st) level or higher priority RF bus request.

When the RF bus resources can be reallocated, the method proceeds tostep 772 where the RF bus controller reallocates at least some of theallocated RF bus resources to make resources available for the 1^(st)level or higher priority RF bus request. The method then proceeds tostep 774 where the RF bus controller 1088 allocates the sufficient RFbus resources to the 1^(st) level or higher priority request.

When the allocated RF bus resources cannot be reallocated and stillprovide an acceptable level of performance, the RF bus controller 1088determines whether the priority of the requestor is of a second prioritylevel (i.e., of the highest level that if its request is not timelysatisfied, the entire system or device may lock up). If the priority isnot at the 2^(nd) level, the method proceeds to step 768 where the RFbus controller 1088 queues the request.

If, however, the priority level of the requestor is of the secondpriority level, the method proceeds to step 778 where the RF buscontroller reclaims RF bus resources from the allocated RF bus resourcesto provide the sufficient RF bus resources. In other words, the RF buscontroller cancels a current RF bus communication to reclaim them forthe 2^(nd) priority level request. In one embodiment, the current RF buscommunication having the most tolerance to a data transmissioninterruption is selected for reclaiming the RF bus resources. The methodthen proceeds to step 780 where the RF bus controller 1088 allocates thereclaimed RF bus resources to the 2^(nd) priority level requestor.

FIG. 55 is a schematic block diagram of another embodiment of amillimeter wave interface 1080 that includes a requestor IC or circuitmodule 790, a target IC or circuit module 792, the RF bus controller1088, a system level RF bus 814, and an application level RF bus 816.The requestor 790 and the target 792 each include an RF bus transceiver974. The RF bus transceiver 794 includes a programmable encode/decodemodule 796, a programmable interleave/deinterleave module 798, aprogrammable map/demap module 800, an inverse fast Fourier transform(IFFT)/FFT module 804, an RF front-end 804, and a plurality ofmultiplexers 806-810. The system level RF bus 814 and the applicationlevel RF bus 816 each include one or more waveguide RF communicationpaths, one or more dielectric RF communication paths, and/or one or morefree-space RF communication paths.

In this embodiment, the RF bus controller 1088 controls access to thesystem level RF bus 814 for operating system level data conveyances andcontrols access to the application level RF bus 816 for applicationlevel data conveyances. Such data conveyances may include controlinformation, operational instructions, and/or data (e.g., raw data,intermediate data, processed data, and/or stored data that includes textinformation, numerical information, video files, audio files, graphics,etc.).

In addition to controlling access to the RF buses 814 and 816, the RFbus controller 1088 may indicate to the RF bus transceivers 794 the RFbus protocol to be used for converting outbound data into outbound RFbus signals. For example, the RF bus protocol may be a standardizedwireless protocol (e.g., IEEE 802.11, Bluetooth, GSM, EDGE, GPRS, CDMA,etc.), may be a proprietary wireless protocol, or a modified standardwireless protocol.

For example, if the RF bus controller 1088 indicates using a standardIEEE 802.11 wireless protocol (e.g., IEEE 802.11a, b, g, n, etc.), theRF bus transceiver 794 enables the programmable modules 796, 798, and800 and the multiplexers 806-810 to perform in accordance with the IEEE802.11 standard. For instance, multiplexer 806 provides outbound data tothe programmable encoding/decoding module 706 that performs a half rate(or other rate) convolution encoding on the outbound data to produceencoded data. The programmable encoding/decoding module 706 may furtherpuncture the encoded data to produce punctured data.

Continuing with the example, the encoded or punctured data is outputtedto multiplexer 808, which provides the data to the programmableinterleave/deinterleave module 708. The programmableinterleave/deinterleave module 708 interleaves bits of different encodeddata words to produce interleaved data. Multiplexer 810 provides theinterleaved data to the programmable map/demap module 800 which maps theinterleaved data to produce mapped data. The mapped data is convertedfrom the frequency domain to the time domain by the IFFT portion of theIFFT/FFT module 802 to produce an outbound symbol stream. Multiplexer810 provides the outbound symbol stream to the RF front end 804, whichincludes an RF transmitter section and an RF receiver section. The RFtransmitter section converts the outbound symbol stream into an outboundRF bus signal.

The target 792 receives the outbound RF bus signal via the system levelRF bus 814 or the application level RF bus 816 via its RF bustransceiver 794. The receiver section of the RF front end 804 convertsthe received RF bus signal into an inbound symbol stream. The FFTportion of the IFFT/FFT module 802 converts the inbound symbol streamfrom the time domain to the frequency domain to produce inbound mappeddata. The programmable map/demap module 800 demaps the inbound mappeddata to produce inbound interleaved data. Multiplexer 810 provides theinbound interleaved data to the programmable interleave/deinterleavemodule 798, which deinterleaves the inbound interleaved data to produceencoded or punctured data. The programmable encoding/decoding module 796depunctures and/or decodes the encoded or punctured data to recapturethe data.

As an example of a modified standard wireless protocol, multiplexer 806provides outbound data to the programmable encoding/decoding module 706that performs a half rate (or other rate) convolution encoding on theoutbound data in accordance with a standard wireless protocol (e.g.,IEEE 802.11) to produce encoded data. The programmable encoding/decodingmodule 706 may further puncture the encoded data to produce punctureddata.

Continuing with the example, the encoded or punctured data is outputtedto multiplexer 808, which provides the data to the programmablemap/demap module 800 which maps the encoded or punctured data to producemapped data. The mapped data is converted from the frequency domain tothe time domain by the IFFT portion of the IFFT/FFT module 802 toproduce an outbound symbol stream. Multiplexer 810 provides the outboundsymbol stream to the RF transmitter section, which converts the outboundsymbol stream into an outbound RF bus signal. As illustrated by thisexample, a modified standard wireless protocol is based on a standardwireless protocol with one or more of its functional steps omitted ormodified.

As another example of a modified standard wireless protocol, multiplexer806 provides outbound data to the programmable map/demap module 800which maps the outbound data to produce mapped data. The mapped data isconverted from the frequency domain to the time domain by the IFFTportion of the IFFT/FFT module 802 to produce an outbound symbol stream,which is subsequently converted into the outbound RF bus signal.

As an example of a proprietary RF bus protocol, multiplexer 806 providesoutbound data to the programmable encoding/decoding module 706 thatperforms a bi-phase, return to zero (RTZ), non-return to zero (NRZ),and/or another binary encoding scheme to produce binary encoded data.The binary encoded data may be provided directly to the RF front end 804via multiplexers 808 and 812, to the programmableinterleave/deinterleave module 798 via multiplexer 808, or to theprogrammable map/demap module 800 via multiplexers 808 and 810.

The programmable map/demap module 800 may be programmed to map/demapdata in a variety of ways. For example, the programmable map/demapmodule 800 may map the data into Cartesian coordinates having anin-phase component (e.g., A_(I)(t)cos ω(t)) and a quadrature component(e.g., A_(Q)(t)sin ω(t)). As another example, the programmable map/demapmodule 800 may map the data into polar coordinates (e.g.,A(t)cos(ω(t)+φ(t))). As yet another example, the programmable map/demapmodule 800 may map the data into hybrid coordinates having a normalizedin-phase component (e.g., cos(ω(t)+φ(t)) and a normalized quadraturecomponent (e.g., sin(ω(t)+φ(t))).

FIG. 56 is a logic diagram of another method for controlling access toan RF bus. The method begins at step 818 where the RF bus controllerdetermines access requirements to an RF bus. The access requirements mayinclude system configuration information, system level RF bus resources,application level RF bus resources, RF bus capabilities of requestor, RFbus capabilities of target, amount of information to be conveyed,priority level of requestor, priority level of the information to beconveyed, real-time or non-real-time aspect of the information to beconveyed, and/or information conveyance integrity requirements.

The system configuration information includes number of ICs in thedevice, number of circuit modules in the ICs, nulling and reinforcingpatterns, number and type of intra-device RF data bus, number and typeof intra-device RF instruction bus, number and type of intra-device RFcontrol bus, number and type of intra-IC RF data bus, number and type ofintra-IC RF instruction bus, number and type of intra-IC RF control bus,types of ICs in the device, and/or bus interface capabilities of the ICsand/or its circuit modules. Note that the information conveyanceintegrity requirements include level of rate encoding (e.g., ½ rate, ¾rate, etc.), level of interleaving, level of error correction, and/orlevel of acknowledgement (e.g., whether an ACK back is required or not,if required content of the ACK). Further note that the system level RFbus resources and the application level RF bus resources includes aSingle Input Single Output (SISO) channel, a Multiple Input MultipleOutput (MIMO) channel, multiple SISO channels, multiple MIMO channels,null-reinforce multipath patterning, frequency band selection, waveguideRF path, dielectric RF path, free space RF path, time division multipleaccess (TDMA) time slot, frequency division multiple access (FDMA)frequency slot, code division multiple access (CDMA) code slot,proprietary resource, and carrier sense multiple access (CSMA).

The method then proceeds to step 820 where the RF bus controllerdetermines RF bus resource available. This step may further includedetermining an RF bus protocol based on the access request, wherein theRF bus protocol is one of: a standardized wireless protocol, aproprietary wireless protocol, and a modified standardized wirelessprotocol.

The method then proceeds to step 822 where the RF bus controllerallocates, via the interface, RF bus resources in accordance with theaccess requirements and the RF bus resource availability. This may bedone by determining whether sufficient RF bus resources are available tofulfill the access requirements; when the sufficient RF bus resourcesare available to fulfill the access request, allocating the sufficientRF bus resources to a requestor; when the sufficient RF bus resourcesare not available to fulfill the access request, determining availableRF bus resources; determining whether the access requirements can beaccommodated by the available RF bus resources; when the access requestcan be accommodated by the available RF bus resources, allocating theavailable RF bus resources to the requestor; and when the access requestcannot be accommodated by the available RF bus resources, queuing theaccess requirements.

The method may further include, when the sufficient RF bus resources arenot available to fulfill the access requirements, the RF bus controllerdetermining whether priority of the requestor is at or above a firstpriority level; when priority of the requestor is at or above the firstpriority level, determining whether allocated RF bus resources can bereallocated to make available the sufficient RF bus resources; when theallocated RF bus resources can be reallocated, reallocating at leastsome of the allocated RF bus resources; when the RF bus resources cannotbe reallocated, determining whether the priority of the requestor is ofa second priority level; when the priority level of the requestor is ofthe second priority level, reclaiming RF bus resources from theallocated RF bus resources to provide the sufficient RF bus resources;and when the priority level of the requestor is below the secondpriority level, queuing the access requirements.

FIG. 57 is a logic diagram of another method for controlling access toan RF bus. The method begins at step 824 where the RF bus controllerdetermines access requirements to an RF bus for a circuit of anintegrated circuit (IC) of a plurality of integrated circuits. This maybe done as previously discussed. The method then proceeds to step 826where the RF bus controller determines whether the access requirementspertain to an inter-IC communication or an intra-IC communication.

The method then proceeds to step 828 where the RF bus controller 1088determines RF bus resource available in accordance with inter-ICcommunication or the intra-IC communication. This may be done aspreviously described. The method then proceeds to step 830 where the RFbus controller allocates, via the interface, RF bus resources inaccordance with the access requirements and the RF bus resourceavailability.

FIG. 58 is a schematic block diagram of an embodiment of an RF bustransceiver 840 that may be used as or in combination with one or moreof the RF bus transceivers or other transceivers previously described.The RF bus transceiver 840 includes a transmitter 842 and a receiver844. The transmitter 842 and the receiver 844 performs one or moremethods of the present invention.

FIG. 59 is a logic diagram of method for RF bus transmitting that beginsat step 846 where the transmitter 842 determine whether outboundinformation is to be transmitted via the RF bus. Such a determinationmay be made by setting a flag by the IC or circuit module that includesthe RF bus transceiver, by providing the outbound information to the RFbus transceiver, and/or any other mechanism for notifying that it hasinformation to transmit.

When the outbound information is to be transmitted via the RF bus, themethod proceeds to step 848 where the transmitter 842 determines whetherthe RF bus is available. When the RF bus is not available, thetransmitter 842 waits until the RF bus becomes available. Thetransmitter 842 may determine by the availability of the RF bus byutilizing a carrier sense multiple access with collision avoidance(CSMA/CD) access protocol, utilizing a request to send frame and clearto send frame exchange access protocol, utilizing a poll-response accessprotocol, interpreting a control time slot of a time division multipleaccess (TDMA) frame, interpreting a control frequency slot of afrequency division multiple access (FDMA) frame, interpreting a controlcode slot of a code division multiple access (CDMA) frame, and/orutilizing a request-grant access protocol.

When the RF bus is available, the method proceeds to step 850 where thetransmitter 842 secures access to the RF bus. The transmitter 842 maysecure access to the RF bus by accessing the RF bus in accordance with acarrier sense multiple access with collision avoidance (CSMA/CD) accessprotocol, accessing the RF bus in response to a favorable request tosend frame and clear to send frame exchange, accessing the RF bus inaccordance with a poll-response access protocol, accessing the RF busvia an allocated time slot of a time division multiple access (TDMA)frame, accessing the RF bus via an allocated frequency slot of afrequency division multiple access (FDMA) frame, accessing the RF busvia an allocated code slot of a code division multiple access (CDMA)frame, and/or accessing the RF bus in accordance with a request-grantaccess protocol. Note that the transmitter 842 may determine whether theRF bus is available and secures access to the RF bus by communicatingwith the RF bus controller 1088 via a wireline link, via a wirelesslink, and/or via the RF bus.

The method proceeds to step 852 where the transmitter 842 converts theoutbound information into outbound RF bus signal. The method thenproceeds to step 844 where the transmitter 842 transmits the outbound RFbus signal via the RF bus when access to the RF bus is secured. As such,the transmitter 842 prepares data for transmission via one of the RFbuses in a device and transmits the RF bus signal when it is thetransmitter's turn and/or when the RF bus is not in use.

FIG. 60 is a logic diagram of method for RF bus receiving that begins atstep 856 where the receiver 844 determines whether inbound informationis to be received via the RF bus. The receiver 844 may determine thatthere is inbound information to be received by utilizing a carrier sensemultiple access with collision avoidance (CSMA/CD) access protocol,utilizing a request to send frame and clear to send frame exchangeaccess protocol, utilizing a poll-response access protocol, interpretinga control time slot of a time division multiple access (TDMA) frame,interpreting a control frequency slot of a frequency division multipleaccess (FDMA) frame, interpreting a control code slot of a code divisionmultiple access (CDMA) frame, and/or utilizing a request-grant accessprotocol.

When there is inbound information to be received via the RF bus, themethod proceeds to step 858 where the receiver 844 determines accessparameters to the RF bus for receiving the inbound information. Thereceiver 844 may determine the access parameters by receiving theinbound RF bus signal in accordance with a carrier sense multiple accesswith collision avoidance (CSMA/CD) access protocol, receiving theinbound RF bus signal in accordance with a request to send frame andclear to send frame exchange, receiving the inbound RF bus signal inaccordance with a poll-response access protocol, receiving the inboundRF bus signal via an allocated time slot of a time division multipleaccess (TDMA) frame, receiving the inbound RF bus signal via anallocated frequency slot of a frequency division multiple access (FDMA)frame, receiving the inbound RF bus signal via an allocated code slot ofa code division multiple access (CDMA) frame, and/or receiving theinbound RF bus signal in accordance with a request-grant accessprotocol. Note that the receiver 844 may determine the access parametersby communicating with the RF bus controller 1088 via a wireline link, awireless link, and/or the RF bus.

The method then proceeds to step 860 where the receiver 844 receives aninbound RF bus signal during the access to the RF bus in accordance withthe access parameters. The method then proceeds to step 862 where thereceiver 844 converts the inbound RF bus signal into the inboundinformation.

FIG. 61 is a logic diagram of method for determining whether informationis to be transmitted via an RF bus by the transmitter 842. The methodbegins at step 870 where the transmitter 842 identifies a target of theoutbound information. In one embodiment, the outbound information willbe in packet or frame format having a header portion that includes theaddress of the source, the address of the destination, the size of thepacket or frame, etc.

The method then proceeds to step 872 where the transmitter 842determines whether the target is accessible via the RF bus. The targetmay not be accessible via the RF bus for several reasons. For example,the nature of the data being transmitted may require that it betransmitted via a wireline link, the target may be in a multipath nullwith respect to the source, the target is currently using the RF bus foranother RF bus communication, etc. When the target is not accessible viathe RF bus, the method proceeds to step 876 where the transmitter 842sends the outbound information via a wireline link.

When the target is accessible via the RF bus, the method proceeds tostep 874 where the transmitter determines the type of the outboundinformation to be transmitted. When the type of the outbound informationis of a first type (e.g., tolerant of transmission errors), the methodproceeds to step 878 where the transmitter 842 indicates that theoutbound information is to be transmitted via the RF bus. When the typeof the outbound information is of a second type (e.g., not tolerant oftransmission errors), the method proceeds to step 876 where thetransmitter 842 indicates that the outbound information is to betransmitted via a wireline link. Note that step 874 could be omitted.

FIG. 62 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-61. In step 900, a first inductive interface ofa first integrated circuit and a second inductive interface of a secondintegrated circuit are aligned. In step 904, signals are magneticallycommunicated between a first circuit of the first integrated circuit anda second circuit of the second integrated circuit via the firstinductive interface and the second inductive interface.

In an embodiment of the present invention, step 904 includesbidirectionally communicating signals between the first circuit and thesecond circuit. Step 900 can include stacking the first integratedcircuit and the second integrated circuit and/or aligning a first coilof the first inductive interface with a second coil of the secondinductive interface.

FIG. 63 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-61 and in particular with the method of claim62. In step 902, the first integrated circuit is bonded to the secondintegrated circuit using a ferromagnetic glue.

FIG. 64 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-63. In step 910, a first inductive interface ofa first integrated circuit die and a second inductive interface of asecond integrated circuit die are aligned. In step 914, signals aremagnetically communicated between a first circuit of the firstintegrated circuit die and a second circuit of the second integratedcircuit die via the first inductive interface and the second inductiveinterface.

In an embodiment of the present invention, step 914 includesbidirectionally communicating signals between the first circuit and thesecond circuit. Step 910 can include stacking the first integratedcircuit and the second integrated circuit and/or aligning a first coilof the first inductive interface with a second coil of the secondinductive interface.

FIG. 65 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-63 and in particular, the method of claim 64.In step 912, the first integrated circuit die is bonded to the secondintegrated circuit die.

FIG. 66 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-65. In step 920, a first inductive interface ofa first integrated circuit die and a second inductive interface of asecond integrated circuit die are aligned with a magnetic communicationpath included in a substrate. In step 924, signals are magneticallycommunicated between a first circuit of the first integrated circuit dieand a second circuit of the second integrated circuit die via the firstinductive interface and the second inductive interface and via themagnetic communication path.

Step 920 can include aligning a third coil of the magnetic communicationpath with a first coil of the first integrated circuit die and aligninga fourth coil of the magnetic communication path with a second coil ofthe first integrated circuit die. Further step 920 can include planarlyaligning a third coil of the magnetic communication path with a firstcoil of the first integrated circuit die, planarly aligning a fourthcoil of the magnetic communication path with a second coil of the firstintegrated circuit die, axially aligning a third coil of the magneticcommunication path with a first coil of the first integrated circuitdie, and/or axially aligning a fourth coil of the magnetic communicationpath with a second coil of the first integrated circuit die. Themagnetic communication path can include a ferromagnetic material. Step924 can include bidirectionally communicating signals between the firstcircuit and the second circuit.

FIG. 67 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-65 and in particular with the method of claim66. In step 922, the first integrated circuit die is bonded to thesubstrate via a ferromagnetic glue.

FIG. 68 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-67 and in particular with the method of claim66. In step 922, the second integrated circuit die is bonded to thesubstrate via a ferromagnetic glue.

FIG. 69 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-68. In step 930, first signals are communicatedbetween a first plurality of integrated circuit dies of an integratedcircuit via corresponding millimeter wave interfaces. In step 932 secondsignals are communicated between a second plurality of integratedcircuit dies of the integrated circuit via corresponding inductiveinterfaces.

In an embodiment of the present invention, at least one of the firstplurality of integrated circuit dies is included in the second pluralityof integrated circuit dies. Further, two or more of the first pluralityof integrated circuit dies can be included in the second plurality ofintegrated circuit dies.

FIG. 70 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-69. In step 934, third signals are communicatedbetween at least one of the first plurality of integrated circuit diesand a remote device via the corresponding millimeter wave interface.

FIG. 71 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-70. In step 940, first signals are communicatedbetween a first plurality of integrated circuits via correspondingmillimeter wave interfaces. In step 942, second signals are communicatedbetween a second plurality of integrated circuits via correspondinginductive interfaces.

In an embodiment of the present invention, at least one of the firstplurality of integrated circuits is included in the second plurality ofintegrated circuits. Further, two or more of the first plurality ofintegrated circuits can be included in the second plurality ofintegrated circuits.

FIG. 72 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-71. In step 944, third signals are communicatedbetween at least one of the first plurality of integrated circuits and aremote device via the corresponding millimeter wave interface.

FIG. 73 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-72. In step 950, first signals are magneticallycommunicated between a first integrated circuit and a second interfacecircuit via a first inductive interface and a second inductiveinterface. In step 952, near field communicates are engaged in via thesecond inductive interface with a remote device, wherein the near fieldcommunications include second signals.

In an embodiment of the present invention, the first signals aremagnetically communicated in a first frequency band and the near fieldcommunications are communicated in a second frequency band that isdifferent from the first frequency band. Steps 950 and 952 can beperformed serially or contemporaneously.

FIG. 74 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-74. In step 60, first signals are magneticallycommunicated between a first integrated circuit die and a secondinterface circuit die via a first inductive interface and a secondinductive interface. In step 962, near field communications are engagedin via the second inductive interface with a remote device, wherein thenear field communications include second signals.

In an embodiment of the present invention, the first signals aremagnetically communicated in a first frequency band and the near fieldcommunications are communicated in a second frequency band that isdifferent from the first frequency band. Steps 960 and 962 can beperformed serially or contemporaneously.

FIG. 75 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-74. In step 970, signals are magneticallycommunicated between a plurality of integrated circuit dies inaccordance with a multi access protocol.

In an embodiment of the present invention, the signals are communicatedvia an RF bus. Step 970 can include arbitrating access to the RF bus.Arbitrating the access to the RF bus can include: receiving an RF busaccess request; determining RF bus resource availability; determiningwhen sufficient RF bus resources are available; and allocating at leastone RF bus resource when sufficient RF bus resources are available.Arbitrating the access to the RF bus can include: polling the pluralityof inductive interfaces; and allocating at least one RF bus resource inresponse to poll. Arbitrating the access to the RF bus can include:receiving a request to reserve at least one RF bus resource from one ofthe plurality of inductive interfaces; and reserving the at least one RFbus resource. The multiple access protocol includes one of: a timedivision multiple access protocol, a frequency division multiple accessprotocol, a random access protocol and a code division multiple accessprotocol. Step 970 can include communicating the signals between aplurality of integrated circuit dies include communicating the signalsbidirectionally.

FIG. 76 is a flowchart representation of a method in accordance with anembodiment of the present invention. In particular a method is shown foruse in conjunction with one or more functions and features described inconjunction with FIGS. 1-75. In step 980, signals are magneticallycommunicated between a plurality of integrated circuits in accordancewith a multi access protocol.

In an embodiment of the present invention, the signals are communicatedvia an RF bus. Step 980 can include arbitrating access to the RF bus.Arbitrating the access to the RF bus can include: receiving an RF busaccess request; determining RF bus resource availability; determiningwhen sufficient RF bus resources are available; and allocating at leastone RF bus resource when sufficient RF bus resources are available.Arbitrating the access to the RF bus can include: polling the pluralityof inductive interfaces; and allocating at least one RF bus resource inresponse to poll. Arbitrating the access to the RF bus can include:receiving a request to reserve at least one RF bus resource from one ofthe plurality of inductive interfaces; and reserving the at least one RFbus resource. The multiple access protocol includes one of: a timedivision multiple access protocol, a frequency division multiple accessprotocol, a random access protocol and a code division multiple accessprotocol. Step 980 can include communicating the signals between aplurality of integrated circuit dies include communicating the signalsbidirectionally.

As may be used herein, the terms “substantially” and “approximately”provides an industry-accepted tolerance for its corresponding termand/or relativity between items. Such an industry-accepted toleranceranges from less than one percent to fifty percent and corresponds to,but is not limited to, component values, integrated circuit processvariations, temperature variations, rise and fall times, and/or thermalnoise. Such relativity between items ranges from a difference of a fewpercent to magnitude differences. As may also be used herein, theterm(s) “coupled to” and/or “coupling” and/or includes direct couplingbetween items and/or indirect coupling between items via an interveningitem (e.g., an item includes, but is not limited to, a component, anelement, a circuit, and/or a module) where, for indirect coupling, theintervening item does not modify the information of a signal but mayadjust its current level, voltage level, and/or power level. As mayfurther be used herein, inferred coupling (i.e., where one element iscoupled to another element by inference) includes direct and indirectcoupling between two items in the same manner as “coupled to”. As mayeven further be used herein, the term “operable to” indicates that anitem includes one or more of power connections, input(s), output(s),etc., to perform one or more its corresponding functions and may furtherinclude inferred coupling to one or more other items. As may stillfurther be used herein, the term “associated with”, includes directand/or indirect coupling of separate items and/or one item beingembedded within another item. As may be used herein, the term “comparesfavorably”, indicates that a comparison between two or more items,signals, etc., provides a desired relationship. For example, when thedesired relationship is that signal 1 has a greater magnitude thansignal 2, a favorable comparison may be achieved when the magnitude ofsignal 1 is greater than that of signal 2 or when the magnitude ofsignal 2 is less than that of signal 1.

While the transistors in the above described figure(s) is/are shown asfield effect transistors (FETs), as one of ordinary skill in the artwill appreciate, the transistors may be implemented using any type oftransistor structure including, but not limited to, bipolar, metal oxidesemiconductor field effect transistors (MOSFET), N-well transistors,P-well transistors, enhancement mode, depletion mode, and zero voltagethreshold (VT) transistors.

The present invention has also been described above with the aid ofmethod steps illustrating the performance of specified functions andrelationships thereof. The boundaries and sequence of these functionalbuilding blocks and method steps have been arbitrarily defined hereinfor convenience of description. Alternate boundaries and sequences canbe defined so long as the specified functions and relationships areappropriately performed. Any such alternate boundaries or sequences arethus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid offunctional building blocks illustrating the performance of certainsignificant functions. The boundaries of these functional buildingblocks have been arbitrarily defined for convenience of description.Alternate boundaries could be defined as long as the certain significantfunctions are appropriately performed. Similarly, flow diagram blocksmay also have been arbitrarily defined herein to illustrate certainsignificant functionality. To the extent used, the flow diagram blockboundaries and sequence could have been defined otherwise and stillperform the certain significant functionality. Such alternatedefinitions of both functional building blocks and flow diagram blocksand sequences are thus within the scope and spirit of the claimedinvention. One of average skill in the art will also recognize that thefunctional building blocks, and other illustrative blocks, modules andcomponents herein, can be implemented as illustrated or by discretecomponents, application specific integrated circuits, processorsexecuting appropriate software and the like or any combination thereof.

What is claimed is:
 1. A method comprising: communicating first signals between a first integrated circuit die of an integrated circuit and a second integrated circuit die of the integrated circuit via a first millimeter wave intra-chip communication transceiver of the first integrated circuit die and a second millimeter wave intra-chip communication transceiver of the second integrated circuit die; communicating second signals between the first integrated circuit die of the integrated circuit and the second integrated circuit die of the integrated circuit via a first inductive intra-chip communication transceiver of the first integrated circuit die and a second inductive intra-chip communication transceiver of the second integrated circuit die.
 2. The method of claim 1 wherein the first integrated circuit die is stacked on the second integrated circuit die so that the second inductive intra-chip communication transceiver is aligned with the first inductive intra-chip communication transceiver.
 3. The method of claim 1 wherein the second signals are communicated via a magnetic communication path of a substrate of the integrated circuit.
 4. The method of claim 1 further comprising: facilitating the communication of the first signals via an RF bus.
 5. The method of claim 3 further comprising: communicating third signals with a remote device via the RF bus.
 6. A method comprising: communicating first signals between a first integrated circuit die of an integrated circuit and a second integrated circuit die of the integrated circuit via a first millimeter wave interface of the first integrated circuit die of the integrated circuit and a second millimeter wave interface of the second integrated circuit die of the integrated circuit; and communicating second signals between the second integrated circuit die of the integrated circuit and a third integrated circuit die of the integrated circuit a first inductive interface of the first integrated circuit die of the integrated circuit and a second inductive interface of the third integrated circuit die of the integrated circuit.
 7. The method of claim 6 wherein the third integrated circuit die is stacked on the second integrated circuit die so that the second inductive intra-chip communication transceiver is aligned with the first inductive intra-chip communication transceiver.
 8. The method of claim 6 wherein the second signals are communicated via a magnetic communication path of a substrate of the integrated circuit.
 9. The method of claim 6 further comprising: facilitating the communication of the first signals via an RF bus.
 10. The method of claim 9 further comprising: communicating third signals with a remote device via the RF bus.
 11. A method comprising: communicating first signals between a first plurality of integrated circuit dies of an integrated circuit via corresponding millimeter wave interfaces; and communicating second signals between a second plurality of integrated circuit dies of the integrated circuit via corresponding inductive interfaces.
 12. The method of claim 11 wherein at least one of the first plurality of integrated circuit dies is included in the second plurality of integrated circuit dies.
 13. The method of claim 11 wherein the at least two of the first plurality of integrated circuit dies is included in the second plurality of integrated circuit dies.
 14. The method of claim 11 further comprising: communicating third signals between at least one of the first plurality of integrated circuit dies and a remote device via the corresponding millimeter wave interface.
 15. The method of claim 11 wherein the second signals are communicated via a magnetic communication path of a substrate of the integrated circuit.
 16. A method comprising: communicating first signals between a first plurality of integrated circuits via corresponding millimeter wave interfaces; and communicating second signals between a second plurality of integrated circuits via corresponding inductive interfaces; wherein at least one of the first plurality of integrated circuits is included in the second plurality of integrated circuits.
 17. The method of claim 16 wherein the at least two of the first plurality of integrated circuits is included in the second plurality of integrated circuits.
 18. The method circuit of claim 16 further comprising: communicating third signals between at least one of the first plurality of integrated circuits and a remote device via the corresponding millimeter wave interface.
 19. The method of claim 16 further comprising: facilitating the communication of the first signals via an RF bus.
 20. The method of claim 19 further comprising: communicating third signals with a remote device via the RF bus. 